北京正负电子对撞机次级束质子单粒子翻转计算和试验研究

北京正负电子对撞机(BEPC)电子直线加速器试验束打靶产生的次级束中包含质子,其中能量约为50MeV~100MeV的质子占有很大比例,这弥补了国内高能质子源的空白。本工作计算得到次级束中的质子能谱,建立质子单粒子翻转截面计算方法,在北京正负电子对撞机次级束质子辐射环境中,计算静态随机存取存储器的质子单粒子翻转截面,设计了SRAM质子单粒子翻转截面测试试验,发现SRAM单粒子翻转和注量有良好的线性,这是SRAM发生单粒子翻转的证据。统计得到不同特征尺寸下SRAM单粒子翻转截面,试验数据与计算结果相符,计算和试验结果表明随着器件特征尺寸的减小器件位单粒子翻转截面减小,但器件容量的增大,翻转截面依然增大,BEPC次级束中的质子束可以开展中高能质子单粒子效应测试。     

温度对SRAM器件单粒子翻转重离子测试的影响

本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上（HIRLF）研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。     

Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

Computer simulations with the Spectre circuit simulator from Cadence Design Systems and a proton-accelerator experiment are conducted to investigate the relationship of single-event-upset (SEU) susceptibility to memory-cell layout in the context of a 0.18-μm CMOS SRAM using the dual interlocked storage cell (DICE) technology with differing separations of the pair transistors designed to store a 0 or 1, namely, 0.9 and 2.5 μm, respectively. The simulated values of critical charge for an upset are found to be greater by a factor of 10 for the wider separation. With 1-GeV proton irradiation, using the wider separation of pair transistors is found to reduce the SEU count by a factor of 5.5–15 (depending on the supply voltage). In the experiment, lowering the supply voltage of the memory bank from 1.8 to 0.7 V is found to increase on average the SEU cross section by a factor of 3. Close agreement is observed between the simulated and measured results.     

One-Parameter Model for the Estimation of IC Susceptibility to Proton-Induced Single-Event Upsets

Singe-event upsets (SEUs) caused by high-energy protons are considered. An analytical model is proposed to represent the dependence of SEU cross section on proton energy. The model is based on a simple mechanism of proton-induced nuclear reactions in silicon. A computer simulation is conducted by the model. The results are found to agree with previous experiments. They indicate that the model enables one to predict susceptibility to proton-induced SEUs on the basis of a single value of SEU cross section measured at a proton energy higher than 100 MeV. It is shown that the approach may also work for heavy ions.     

SRAM single event upset calculation and test using protons in the secondary beam in the BEPC

The protons in the secondary beam in the Beijing Electron Positron Collider(BEPC) are first analyzed and a large proportion at the energy of 50-100 MeV supply a source gap of high energy protons.In this study, the proton energy spectrum of the secondary beam was obtained and a model for calculating the proton single event upset(SEU) cross section of a static random access memory(SRAM) cell has been presented in the BEPC secondary beam proton radiation environment.The proton SEU cross section for different characteristic dimensions has been calculated.The test of SRAM SEU cross sections has been designed,and a good linear relation between SEUs in SRAM and the fluence was found,which is evidence that an SEU has taken place in the SRAM.The SEU cross sections were measured in SRAM with different dimensions.The test result shows that the SEU cross section per bit will decrease with the decrease of the characteristic dimensions of the device,while the total SEU cross section still increases upon the increase of device capacity.The test data accords with the calculation results,so the high-energy proton SEU test on the proton beam in the BEPC secondary beam could be conducted.     

A new NMOS temperature-stable voltage reference

An NMOS voltage reference has been developed that exhibits extremely low drift with temperature. The reference is based on the difference between the gate/source voltages of enhancement and depletion-mode NMOS transistors. The theoretical dependence of the reference voltage on both device and circuit parameters is analyzed and conditions for optimal performance are derived. The reference NMOS transistors are biased to the optimizing current levels by a unique feedback circuit. The measured output voltage drift in the integrated realization agrees well with theory and is less than 5 parts per million per degree Celsius over the temperature range -55/spl deg/ to +125/spl deg/C.     

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are examined. The radiation tests are performed at ⁶⁰Co sources at the dose rate of 50 rad (Si)/s. The investigation''s results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation structure is the main total dose problem. The total ionizing dose (TID) radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is established. The I-V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I-V characteristics of 180 nm commercial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.     

小尺寸NMOS和PMOS SEU敏感性对比分析

使用软件模拟的方法对NMOS和PMOS的单粒子翻转(SEU)特性进行份真,通过在阱内外碰撞的两种情况下对小尺寸NMOS和PMOS的SEU敏感性进行对比可知,对于深亚微米阶段相同工艺的器件,在阱外碰撞时,NMOS一定比PMOS对SEU敏感;但对于阱内碰撞,NMOS和PMOS对SEU的敏感性要视具体情况而定.     

Experimental research of heavy ion and proton induced single event effects for a Bi-CMOS technology DC/DC converter

This paper tested and analyzed heavy ion and proton induced single event effects (SEE) of a commercial DC/DC converter based on a 600 nm Bi-CMOS technology. Heavy ion induced single event transients (SET) testing has been carried out by using the Beijing HI-13 tandem accelerator at China Institute of Atomic Energy. Proton test has been carried out by using the Canadian TRIUMF proton accelerator. Both SET cross section versus linear energy transfer (LET) and proton energy has been measured. The main study conclusions are: (1) the DC/DC is both sensitive to heavy ion and proton radiations although at a pretty large feature size (600 nm), and threshold LET is about 0.06 MeV·mg/cm²; (2) heavy ion SET saturation cross section is about 5 magnitudes order larger than proton SET saturation cross section, which is consistent with the theory calculation result deduced by the RPP model and the proton nuclear reaction model; (3) on-orbit soft error rate (SER) prediction showed, on GEO orbit, proton induced SERs calculated by the heavy ion derived model are 4-5 times larger than those calculated by proton test data.     

Proton-induced SEU in SiGe digital logic at cryogenic temperatures

We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63 MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300 K to 77 K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50 Mbit/s to 4 Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300 K and 77 K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2 D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300 K and 77 K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures.     

An enhanced MOSFET threshold voltage model for the 6–300 K temperature range

An enhanced threshold voltage model for MOSFETs operating over a wide range of temperatures (6–300K) is presented. The model takes into account the carrier freeze-out effect and the external field-assisted ionization to address the temperature dependence of MOS transistors. For simplicity, an empirical function is incorporated to predict short channel effects over the temperature range. The results from the proposed model demonstrate good agreement with NMOS and PMOS transistors measured from fabricated chips.     

一种基于0.18μm CMOS工艺的上电复位电路

介绍了一种采用0.18μm CMOS工艺制作的上电复位电路。为了满足低电源电压的设计要求,采用低阈值电压(约0V)NMOS管和设计的电路结构,获得了合适的复位电压点;利用反馈结构加速充电,提高了复位信号的陡峭度;利用施密特触发器,增加了电路的迟滞效果。电路全部采用MOS管设计,大大缩小了版图面积。该上电复位电路用于一种数模混合信号芯片,采用0.18μm CMOS工艺进行流片。芯片样品电路测试表明,该上电复位电路工作状态正常。     

Punchthrough behavior in short channel NMOS and PMOS 6H-siliconcarbide transistors at elevated temperatures

An experimental investigation of the effects of high temperature on short channel NMOS and PMOS transistors in 6H-SiC is reported. Punchthrough characteristics are presented and examined at room temperature and 300°C. The punchthrough current increases dramatically for scaled PMOS transistors at high temperature while the temperature dependence of electrical characteristics for short channel NMOS is small. The results presented in this paper also provide insight into design criteria for short channel silicon carbide (SiC) devices intended for operation at elevated temperatures     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

High‐Gain Double‐Bulk Mixer in 65 nm CMOS with 830 pW Power Consumption

A low‐power down‐sampling mixer in a low‐power digital 65 nm CMOS technology is presented. The mixer consumes only 830 µW at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 °1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of ?5.9 dBm is achieved.     

High temperature performance of NMOS integrated inverters and ringoscillators in 6H-SiC

Electrical characterization up to 573 K is performed on integrated inverters with different beta ratios and 17-stage ring oscillators based on SiC NMOS technology. These devices are fabricated on a p-type 6H-SiC epitaxial layer with a doping concentration of N_A=1·10 ¹⁶ cm^-3. The n⁺ source/drain regions and buried channels for depletion-mode load transistors are achieved by ion implantation of nitrogen. Direct current measurements of the inverters with a 5 V power supply yield proper output levels and acceptable noise margins both at 303 and 573 K. Dynamic measurements with square waves show the full voltage swing up to 5 kHz in this temperature range. The 17-stage ring oscillators, driven by a 5.5 V power supply, show an oscillator frequency of 625 kHz at 303 K, which corresponds to a 47 ns delay per inverter stage. This time constant increases only to 59 ns at 573 K. The temperature drift of the measured output signal is well below 30% up to this elevated temperatures. During 20 heat cycles up to 573 K in air, no measurable drift in circuit parameters occurred. In addition, only a slight dependence of the oscillator frequency on supply voltage is observed     

1.0-µm n-well CMOS/bipolar technology

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n⁺-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n⁺-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

A four-quadrant current multiplier/divider cell with four transistors

We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.     

浮栅器件的单粒子翻转效应

基于中国原子能科学研究院的HI-13加速器,利用不同线性能量传输(LET)值的重离子束流对4款来自不同厂家的90 nm特征尺寸NOR型Flash存储器进行了重离子单粒子效应试验研究,对这些器件的单粒子翻转(SEU)效应进行了评估。试验中分别对这些器件进行了静态和动态测试,得到了它们在不同LET值下的SEU截面。结果表明高容量器件的SEU截面略大于低容量的器件;是否加偏置对器件的翻转截面几乎无影响;两款国产替代器件的SEU截面比国外商用器件高。国产替代器件SEU效应的LET阈值在12.9 MeV·cm²/mg附近,而国外商用器件SEU效应的LET阈值处于12.9~32.5 MeV·cm²/mg之间。此外,针对单粒子和总剂量效应对试验器件的协同作用也开展了试验研究,试验结果表明总剂量累积会增加Flash存储器的SEU效应敏感性,分析认为总剂量效应产生的电离作用导致了浮栅上结构中的电子丢失和晶体管阈值电压的漂移,在总剂量效应作用的基础上SEU更容易发生。     

纳米器件质子在轨单粒子翻转率预计方法

研究了纳米器件在空间轨道中质子引起单粒子翻转(SEU)率的预计方法。以65 nm SRAM为样品,利用加速器进行了质子和重离子单粒子翻转试验,分别基于质子试验数据和重离子试验数据,预计了空间轨道中质子引起的单粒子翻转率。结果表明,用重离子试验数据预计的质子单粒子翻转率比用质子试验数据预计的低1.5个数量级。研究认为,为了评估纳米器件单粒子翻转敏感性,需进行质子单粒子翻转试验,并基于质子试验数据进行在轨质子翻转率预计。