Experimental study and modeling of band-to-band tunneling leakage current in thin-oxide MOSFETs

The band-to-band tunneling current in MOS transistors is studied by measuring and simulating the leakage characteristics of devices with an oxide thickness in the range 100–250 Å and different source-drain junctions. In case of conventional As implanted junctions a simple physically based expression for the tunneling leakage current as a function of applied voltage and oxide thickness with empirically matched parameters is derived. A 2-D process and device simulation approach has been used for analysis and reduction of the band-to-band tunneling leakage in conventional DDD and GGO transistors.     

A quantitative analysis of time-decay reproducible stress-inducedleakage current in SiO2 films

In the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress, three reproducible stress-induced leakage current (SILC) components have been found for the repeated unipolar gate-voltage scans in 9.2 nm wet oxides. To clarify the mechanisms of these current components, a quantitative analysis has been developed. By precisely modeling the phonon assisted tunneling process, it has been shown that the E-J and t-J characteristics of the reproducible current components can be completely simulated as electron tunneling processes into the neutral traps, each with a single trap level. From this analysis, the physical parameters of the traps have been estimated with a reasonable degree of accuracy. Furthermore, the increase in distribution of the neutral trap density toward both the SiO₂ interfaces has also been estimated     

A stimulated inelastic tunneling theory of negative differential resistance in metal-insulator-metal diodes

The negative differential resistance that has been observed in the current-voltage characteristics of some metal-insulator-metal (MIM) diodes is investigated theoretically. A refined theory, involving the stimulated inelastic tunneling of electrons through the diode's insulating layer, is developed to explain the negative resistance. Electrons can tunnel inelastically through the insulating layer by emitting surface plasmons. It is shown that if the diode structure forms a resonant cavity of the proper frequency and sufficiently highQ-factor, the effect of emitted plasmons can be contained long enough to stimulate additional inelastic tunneling. Second order perturbation theory is used to derive an equation for the current-voltage characteristic of an MIM diode exhibiting negative differential resistance. Numerical calculations show that aQ-factor of10^{2}-10^{4}is required to match the theoretical results to published current-voltage characteristics of MIM diodes with negative differential resistance.     

Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

Numerical confirmation of inelastic trap-assisted tunneling (ITAT)as SILC mechanism

This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density N_t, and the trap energy level E_t. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are thoroughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build N _t explicitly as a function of the stress electron fluence. Then the overall tunneling probability is calculated, with which a best fitting to SILC I-V furnishes τ of 4.0×10^-13 s and E_t of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

The effect of transition region on the direct tunneling current and Fowler–Nordheim tunneling current oscillations in ultrathin MOS structures

The effects of transition region on direct tunneling and Fowler–Nordheim (FN) tunneling in ultrathin metal–oxide–semiconductor field transistors are investigated by numerical analysis. Direct tunneling current in ultrathin gate oxide is shown to increase with the width of transition region. The applied voltage across the oxide at the maximum and minimum of FN tunneling current oscillations is observed to increase with the width of the transition region, and its relative increase also strongly depends on the width. Furthermore, the amplitude of FN tunneling current oscillations descends with the width of transition region, however, its attenuation factor trends to increase with the width. Usually the amplitude and its attenuation factor decrease with the ordinal number of current oscillation increasing. So the effect of the transition region on FN tunneling current oscillations may be used to extract the information about the transition region.     

Effects of neglecting carrier tunneling on electrostatic potentialin calculating direct tunneling gate current in deep submicron MOSFETs

We investigate the validity of the assumption of neglecting carrier tunneling effects on the self-consistent electrostatic potential in calculating the direct tunneling gate current in deep submicron MOSFETs. A comparison between simulated and experimental results shows that for accurate modeling of direct tunneling current, tunneling effects on potential profile need to be considered. The relative error in gate current due to neglecting carrier tunneling is higher at higher gate voltages and increases with decreasing oxide thickness. We also study the direct tunneling gate current in MOSFETs with high-K gate dielectrics     

An analytical gate tunneling current model for MOSFETs

Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions. Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent agreement with experimental results in the literature.     

Polarity-dependent tunneling current and oxide breakdown indual-gate CMOSFETs

The gate tunneling leakage current in dual-gate CMOSFETs exhibits strong polarity dependence when measured in inversion, although it exhibits practically no polarity dependence when measured in accumulation. Specifically, p⁺-gate pMOSFET shows substantially lower tunneling current than n⁺-gate nMOSFET when measured in inversion. This polarity dependence arises from the difference in the supply of tunneling electrons. The polarity dependent tunneling current has a significant impact on oxide reliability measurements. For example, it gives rise to a higher T_bd value for p⁺/pMOSFET as compared to that for n⁺/nMOSFET when both are biased to inversion. Rationaless are given as to why T_bd is a better gauge than Q_bd for reliability assessment, and why nMOSFET is more prone to oxide breakdown than pMOSFET under normal operating conditions     

Effects of inelastic scattering on interband tunneling inGaSb/AlSb/InAs/GaSb/AlSb/lnAs broken-gap interband tunneling structures

Effects of inelastic scattering on interband tunneling in GaSb/AlSb/InAs/GaSb/AlSb/InAs BGIT's are investigated. The broadening mechanisms due to inelastic scattering are incorporated into the interband tunneling theory. The transmission and reflection coefficients are calculated with the aid of a three-band model, in which the conduction, light-hole, and split-off bands are coupled with one another. It is found that the inelastic scattering lowers the transmission peak and broadens the full-width at half-maximum, resulting in the decrease of the tunneling current. The calculated tunneling current due to inelastic scattering is found to have better agreement with the experiments. In addition, as the valley current plays an important role in the peak-to-valley current ratio (PVR), we then try to deduce the origin of the valley currents. The thermionic current is included in the valley current to estimate the peak-to-valley current ratio. The thermionic component from the GaSb well has important contribution to the valley current in the studied structures. The peak-to-valley current ratio is also estimated and found to have better agreement with the experiment when the inelastic scattering is considered     

Oxide roughness effect on tunneling current of MOS diodes

Two-dimensional (2-D) device simulation is used to investigate the tunneling current of metal ultra-thin-oxide silicon tunneling diodes with different oxide roughness. With the conformal nature of ultrathin oxide, the tunneling current density is simulated in both direct tunneling and Fowler-Nordheim (FN) tunneling regimes with different oxide roughness. The results show that oxide roughness dramatically enhances the tunneling current density and the 2-D electrical effect is responsible for this increment of tunneling current density. Furthermore, a set of devices with controlled oxide roughness is fabricated to verify the simulation results and our model qualitatively agrees with the experiment results.     

Model to predict gate tunneling current of plasma oxynitrides

Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (J/sub g/) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO/sub 2/. It is found that n-MOSFET inversion J/sub g/ is larger than p-MOSFET inversion J/sub g/ when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET J/sub g/ for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for J/sub g/, and we estimate the nitrogen concentration required for each node and application.     

Modeling of direct tunneling current through gate dielectric stacks

The direct tunneling current has been calculated for the first time from an inverted p-substrate through different gate dielectrics by numerically solving Schroedinger's equation and allowing for wavefunction penetration into the gate dielectric stack. The numerical solution adopts a first-order perturbation approach to calculate the lifetime of the quasi-bound states. This approach has been verified to be valid even for extremely thin dielectrics (0.5 nm). The tunneling currents predicted by this technique compare well with the WKB solution. Also for the first time investigation of the wavefunction penetration into gate stacks and their effects on quantization in the substrate has also been performed. For the same effective oxide thickness (EOT) the direct tunneling current decreases with increasing dielectric constant, as expected. However, in order to take full advantage of using high-K dielectrics as gate insulators the interfacial oxide needs to be eliminated     

Explicit model for the gate tunneling current in double-gate MOSFETs

In this paper, we present an explicit compact quantum model for the gate tunneling current in double-gate metal–oxide–semiconductor field-effect transistors (DG-MOSFETs). Specifically, an explicit closed-form expression is proposed, useful for the fast evaluation of the gate leakage in the context of electrical circuit simulators. A benchmarking test against 1D self-consistent numerical solution of Schrödinger–Poisson (SP) equations has been performed to demonstrate the accuracy of the model.     

Analysis of band-to-band tunneling leakage current intrench-capacitor DRAM cells

Evidence demonstrating that the band-to-band tunneling leakage current occurs mainly at the edge of the self-aligned isolation rather than the trench upper corners is presented. Moreover, the leakage current increases drastically with the decrease of capacitor oxide thickness. It is shown that the leakage current limits the thickness of capacitor oxide to more than 80 Å even if the operation voltage is reduced to 3.3 V from 5 V     

Well width dependence of tunneling current in double-quantum-wellresonant interband tunnel diodes

Current-voltage characteristics of double-quantum-well (DQW) resonant interband tunnel (RIT) heterojunction InGaAlAs diodes with well widths of 20, 30, 40, and 60 Å were experimentally investigated at room temperature and compared. Peak current density exhibits a maximum at the 40-Å well width, which is an order of magnitude greater than the peak current densities of other well widths. The calculation of the positions of electronic states leads to the following simple explanation: there are no bound states in the 20- and 30-Å wells. In the 40-Å well, one electronic state appears near the top of the well. This state, which coincides with the Fermi level, is responsible for resonant transmission. In the 60-Å well, the only electronic state is too deep and too far from the Fermi level for resonance to occur     

PD/SOI SRAM performance in presence of gate-to-body tunneling current

This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.     

Identification of a corner tunneling current component in advancedCMOS-compatible bipolar transistors

A corner tunneling current component in the reverse-biased emitter-base junction of advanced CMOS compatible polysilicon self-aligned bipolar transistors has been identified by measuring base current as a function of temperature, bias voltage, and emitter shape. This current is found to be an excess tunneling current caused by an increase in defect density in the corners of the emitter and gives rise to three-dimensional effects in small-geometry devices. The devices used for this study were selected from batches aimed at optimizing the emitter-base system. For this reason, the starting material was n-type (~10¹⁶ cm^-3) and provided the collector regions of the transistors. The intrinsic base and lightly doped extrinsic base regions were both implanted at 30 keV to a dose of 1×10¹³ cm^-2. The activation anneal was performed at 1060°C for 20 s in a rapid thermal annealer. Under such conditions, the emitter-base junction is located about 600 Å below the polysilicon-substrate interface