Application of Feed-forward Artificial Neural Networks to the Identification of Defective Analog Integrated Circuits

This paper presents a new approach for detecting defects in analog integrated circuits using a feed-forward neural network trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting faults in a simple analog CMOS circuit by representing the differences observed in power supply current of fault-free and faulty circuits. The identification of defects was performed in time and frequency domains, followed by a comparison of results achieved in both domains. We show that resilient back-propagation neural networks can be a very efficient and versatile approach for identifying defective analog circuits. Moreover, this approach is not limited to the supply current analysis, because it also offers monitoring of other circuit parameters. The type of defects detected by the resilient backpropagation neural networks, as well as other possible applications of this approach, are discussed.     

一种推挽式电路故障诊断方法的仿真研究

提出了基于小波变换和神经网络的推挽式电路故障诊断方法。先仿真得到各种故障状态下的输出电压信号,然后对输出电压信号进行Daubechies小波变换获取多尺度低频系数和高频系数,并对小波系数进行处理提取故障特征量,最后利用故障特征矢量训练神经网络确定了推挽式电路故障诊断的神经网络模型。仿真结果表明基于小波变换和神经网络的推挽式电路故障诊断方法取得了较好的效果。     

Wavelet based fault detection in analog VLSI circuits using neural networks

This paper deals with a new method of testing analog VLSI circuits, using wavelet transform for analog circuit response analysis and artificial neural networks (ANN) for fault detection. Pseudo-random patterns generated by Linear Feedback Shift Register (LFSR) are used as input test patterns. The wavelet coefficients obtained for the fault-free and faulty cases of the circuits under test (CUT) are used to train the neural network. Two different architectures, back propagation and probabilistic neural networks are trained with the test data. To minimize the neural network architecture, normalization and principal component analysis are done on the input data before it is applied to the neural network. The proposed method is validated with two IEEE benchmark circuits, namely, the operational amplifier and state variable filter.     

基于小波包神经网络的模拟电路故障诊断

提出了基于小波多分辨分析和小波包预处理的模拟电路故障诊断方法。该方法用小波作为信号预处理工具,经小波多分辨分析得到N层分解后的低频和高频信号,再利用小波包分析对多分辨分析没有细分的高频信号进一步分解,以达到提高频率分解率的目的。经PCA分析和归一化后的能量作为训练样本送入BP神经网络进行训练。仿真实验表明此方法能够快速有效的对模拟电路的故障进行诊断和定位。     

基于多频测试和神经网络的模拟电路故障诊断

多频测试使模拟电路响应的故障状态和正常状态差异最大化,而神经网络具有解决复杂分类问题的能力。结合两者优点,提出一种基于多频测试和神经网络的故障诊断方法:通过灵敏度分析指导多频测试矢量生成,选择最优测试激励;提取各测试节点响应的故障信息,利用神经网络对各种状态下的特征向量进行分类决策,实现对故障元件的检测和定位。实验结果表明,该方法对模拟电路故障诊断非常有效,具有很强的实用性。     

Analog Genetic Encoding for the Evolution of Circuits and Networks

This paper describes a new kind of genetic representation called analog genetic encoding (AGE). The representation is aimed at the evolutionary synthesis and reverse engineering of circuits and networks such as analog electronic circuits, neural networks, and genetic regulatory networks. AGE permits the simultaneous evolution of the topology and sizing of the networks. The establishment of the links between the devices that form the network is based on an implicit definition of the interaction between different parts of the genome. This reduces the amount of information that must be carried by the genome, relatively to a direct encoding of the links. The application of AGE is illustrated with examples of analog electronic circuit and neural network synthesis. The performance of the representation and the quality of the results obtained with AGE are compared with those produced by genetic programming.     

A novel neural-network approach of analog fault diagnosis based on kernel discriminant analysis and particle swarm optimization

Kernel principal component analysis (KPCA) and kernel linear discriminant analysis (KLDA) are two commonly used and effective methods for dimensionality reduction and feature extraction. In this paper, we propose a KLDA method based on maximal class separability for extracting the optimal features of analog fault data sets, where the proposed KLDA method is compared with principal component analysis (PCA), linear discriminant analysis (LDA) and KPCA methods. Meanwhile, a novel particle swarm optimization (PSO) based algorithm is developed to tune parameters and structures of neural networks jointly. Our study shows that KLDA is overall superior to PCA, LDA and KPCA in feature extraction performance and the proposed PSO-based algorithm has the properties of convenience of implementation and better training performance than Back-propagation algorithm. The simulation results demonstrate the effectiveness of these methods.     

Software-based rerouting for fault-tolerant pipelined communication

This paper presents a software-based approach to fault-tolerant routing in networks using wormhole or virtual cut-through switching. When a message encounters a faulty output link, it is removed from the network by the local router and delivered to the messaging layer of the local node's operating system. The message passing software can reroute this message, possibly along nonminimal paths. Alternatively, the message may be addressed to an intermediate node, which will forward the message to the destination. A message may encounter multiple faults and pass through multiple intermediate nodes. The proposed techniques are applicable to both obliviously and adaptively routed networks. The techniques are specifically targeted toward commercial multiprocessors where the mean time to repair (MTTR) is much smaller than the mean time between router failures (MTBF), i.e., it is sufficient to tolerate a maximum of three failures. This paper presents requirements for buffer management, deadlock freedom, and livelock freedom. Simulation results are presented to evaluate the degradation in latency and throughput as a function of the number and distribution of faults. There are several advantages of such an approach. Router designs are minimally impacted, and thus remain compact and fast. Only messages that encounter faulty components are affected, while the machine is ensured of continued operation until the faulty components can be replaced. The technique leverages existing network technology, and the concepts are portable across evolving switch and router designs. Therefore, we feel that the technique is a good candidate for incorporation into the next generation of multiprocessor networks     

采用计数器存储权值的人工神经网络的实现

文中提出了一种采用计数器存储权值的人工神经网络的实现方案。数字权值采用计数器存储,突触电路和神经元电路用模拟电路来实现。数字权值经脉冲宽度调制电路转换为脉冲信号作为模拟突触电路的输入信号。因而权值可以长期存储,对权值的修改易于实现,突触神经元电路结构简单,融合了人工神经网络模拟实现和数字实现的优点。对于智能计算机的实现具有重要的意义。     

Time-domain analysis methodology for large-scale RLC circuits and its applications

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts: 1) An approach is proposed to delete all intermediate nodes of RL branches. 2) An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3) The Y toπtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground (P/G) networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.     

Stochastic neural networks

The first purpose of this paper is to present a class of algorithms for finding the global minimum of a continuous-variable function defined on a hypercube. These algorithms, based on both diffusion processes and simulated annealing, are implementable as analog integrated circuits. Such circuits can be viewed as generalizations of neural networks of the Hopfield type, and are called “diffusion machines.” Our second objective is to show that “learning” in these networks can be achieved by a set of three interconnected diffusion machines: one that learns, one to model the desired behavior, and one to compute the weight changes.     

一种模拟电路的支持向量机故障诊断方法

系统地提出了模拟电路的最小二乘小波支持向量机故障诊断方法。从测试点得到各种故障状态下的输出电压信号，对输出电压信号进行小波去噪，对信号进行小波分解获取多尺度的低频系数和高频系数，并对小波系数进行处理从而提取出故障特征量，以此作为学习样本来训练最小二乘小波支持向量机，确定其模拟电路故障诊断的模型。雷达系统电路仿真结果表明了模拟电路的小波变换和最小二乘小波支持向量机故障诊断方法取得了较好的效果。     

基于电流源激励的BP神经网络模拟电路故障诊断

针对传统故障字典法对模拟电路故障诊断时存在的缺陷提出了新的故障字典法;将电流源激励下二端口网络输入端和输出端的电压增益比作为故障特征信息,在此基础上先直流测试,后利用BP神经网络交流测试;该方法充分考虑了电路元件的容差,减轻了BP神经网络诊断故障的负担,提高了故障诊断的速度、准确率以及故障覆盖率;利用MATLAB和PSPICE工具对该方法进行实例仿真,结果表明其能够实现快速、准确的故障定位。     

Neural network recognition of electronic malfunctions

Neural network software can be applied to manufacturing process control as a tool for diagnosing the state of an electronic circuit board. The neural network approach significantly reduces the amount of time required to build a diagnostic system. This time reduction occurs because the ordinary combinatorial explosion in rules for identifying faulted components can be avoided. Neural networks circumvent the combinatorial explosion by taking advantage of the fact that the fault characteristics of multiple simultaneous faults frequently correlate to the fault characteristics of the individual faulted components. This article clearly demonstrates that state-of-the-art neural networks can be used in automatic test equipment for iterative diagnosis of electronic circuit board malfunctions.     

基于Volterra频域核辨识的非线性模拟电路故障诊断

基于Volterra级数时域频域混合模型,提出了辨识非线性模拟电路频域核的故障诊断方法.利用混合模型辨识算法和范德蒙特法估计各种故障状态下电路响应的前3阶频域核,提取故障特征并与相应的故障模式一起构成特征样本集,借助于支持向量机多分类器进行分类识别,实现非线性模拟电路的故障诊断.阐述了诊断原理及诊断步骤,并给出了诊断实例.仿真结果表明,该方法的故障识别率较高,便于计算机计算.     

基于S变换和小波神经网络的容差模拟电路故障诊断

提出了一种结合S变换和小波神经网络的容差模拟电路故障诊断新方法;该方法通过对被测电路的冲激响应进行S变换,提取信号的时频信息做为特征量,并将所提取的特征量做为小波神经网络的输入进行训练并分类;仿真实验结果表明该方法诊断速度快且故障定位准确率高,在噪声影响、故障类型的特征向量重叠率高以及可测节点不足的情况下,具有良好的故障识别效果。     

Tolerance to analog hardware of on-chip learning in backpropagationnetworks

In this paper we present results of simulations performed assuming both forward and backward computation are done on-chip using analog components. Aspects of analog hardware studied are component variability, limited voltage ranges, components (multipliers) that only approximate the computations in the backpropagation algorithm, and capacitive weight decay. It is shown that backpropagation networks can learn to compensate for all these shortcomings of analog circuits except for zero offsets, and the latter are correctable with minor circuit complications. Variability in multiplier gains is not a problem, and learning is still possible despite limited voltage ranges and function approximations. Fixed component variation from fabrication is shown to be less detrimental to learning than component variation due to noise. Weight decay is tolerable provided it is sufficiently small, which implies frequent refreshing by rehearsal on the training data or modest cooling of the circuits. The former approach allows for learning nonstationary problem sets.     

Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks

 Hardware implementation of artificial neural networks (ANN) based on MOS transistors with floating gate (Neuron MOS or νMOS) is discussed. Choosing analog approach as a weight storage rather than digital improves learning accuracy, minimizes chip area and power dissipation. However, since weight value can be represented by any voltage in the range of supplied voltage (e.g. from 0 to 3.3 V), minimum difference of two values is very small, especially in the case of using neuron with large sum of weights. This implies that ANN using analog hardware approach is weak against V _dd deviation. The purpose of this paper is to investigate main parts of analog ANN circuits (synapse and neuron) that can compensate all kinds of deviation and to develop their design methodologies.     

Supervised neural networks for the classification of structures

Standard neural networks and statistical methods are usually believed to be inadequate when dealing with complex structures because of their feature-based approach. In fact, feature-based approaches usually fail to give satisfactory solutions because of the sensitivity of the approach to the a priori selection of the features, and the incapacity to represent any specific information on the relationships among the components of the structures. However, we show that neural networks can, in fact, represent and classify structured patterns. The key idea underpinning our approach is the use of the so called "generalized recursive neuron", which is essentially a generalization to structures of a recurrent neuron. By using generalized recursive neurons, all the supervised networks developed for the classification of sequences, such as backpropagation through time networks, real-time recurrent networks, simple recurrent networks, recurrent cascade correlation networks, and neural trees can, on the whole, be generalized to structures. The results obtained by some of the above networks (with generalized recursive neurons) on the classification of logic terms are presented.     

Toward Optimal Network Fault Correction in Externally Managed Overlay Networks

We consider an end-to-end approach of inferring probabilistic data forwarding failures in an externally managed overlay network, where overlay nodes are independently operated by various administrative domains. Our optimization goal is to minimize the expected cost of correcting (i.e., diagnosing and repairing) all faulty overlay nodes that cannot properly deliver data. Instead of first checking the most likely faulty nodes as in conventional fault localization problems, we prove that an optimal strategy should start with checking one of the candidate nodes, which are identified based on a potential function that we develop. We propose several efficient heuristics for inferring the best node to be checked in large-scale networks. By extensive simulation, we show that we can infer the best node in at least 95 percent of time, and that first checking the candidate nodes rather than the most likely faulty nodes can decrease the checking cost of correcting all faulty nodes.