An FPGA Implementation of High‐Speed Flexible 27‐Mbps 8‐StateTurbo Decoder

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half‐rate turbo decoder designed for binary quadrature phase‐shift keying (B/QPSK) modulation. A transformation applied to the incoming I‐channel and Q‐channel symbols allows the use of an off‐the‐shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix‐4, dual‐path processing, parallel decoding, and early‐stop algorithms. We implement the proposed scheme on a field‐programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.     

Carrier phase recovery for turbo‐coded systems with pre‐coded GMSK modulation

A carrier phase recovery scheme suited for turbo‐coded systems with pre‐coded Gaussian minimum shift keying (GMSK) modulation is proposed and evaluated in terms of bit‐error‐rate (BER) performance. This scheme involves utilizing the extrinsic information obtained from the turbo‐decoder to aid an iterative carrier phase estimation process, based on a maximum‐likelihood (ML) strategy. The phase estimator works jointly with the turbo‐decoder, using the updated extrinsic information from the turbo‐decoder in every iterative decoding. A pre‐coder is used to remove the inherent differential encoding of the GMSK modulation. Two bandwidths of GMSK signals are considered: BT=0.5 and 0.25, which are recommended by the European Cooperation for Space Standardization (ECSS). It is shown that the performance of this technique is quite close to the perfect synchronized system within a wide range of phase errors. This technique is further developed to recover nearly any phase error in [?π,+π] by increasing the number of phase estimators and joint decoding units. This, however, will increase the complexity of the system. Copyright © 2008 John Wiley & Sons, Ltd.     

Design of AT‐DMB Baseband Receiver SoC

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT‐DMB) baseband receiver SoC. The AT‐DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T‐DMB system; therefore, a conventional T‐DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT‐DMB baseband receiver SoC is fabricated using 0.13 µm technology and shows successful operation with a 50 mW power dissipation.     

Performance of multilevel‐turbo codes with blind/non‐blind equalization over WSSUS multipath channels

In this paper, in order to improve error performance, we introduce a new type of turbo codes, called ‘multilevel‐turbo codes (ML‐TC)’ and we evaluate their performance over wide‐sense stationary uncorrelated scattering (WSSUS) multipath channels. The basic idea of ML‐TC scheme is to partition a signal set into several levels and to encode each level separately by a proper component of the turbo encoder. In the considered structure, the parallel input data sequences are encoded by our multilevel scheme and mapped to any modulation type such as MPSK, MQAM, etc. Since WSSUS channels are very severe fading environments, it is needed to pass the received noisy signals through non‐blind or blind equalizers before turbo decoders. In ML‐TC schemes, noisy WSSUS corrupted signal sequence is first processed in equalizer block, then fed into the first level of turbo decoder and the first sequence is estimated from this first Turbo decoder. Subsequently, the other following input sequences of the frame are computed by using the estimated input bit streams of previous levels. Here, as a ML‐TC example, 4PSK 2 level‐turbo codes (2L‐TC) is chosen and its error performance is evaluated in WSSUS channel modelled by COST 207 (Cooperation in the field of Science & Technology, Project #207). It is shown that 2L‐TC signals with equalizer blocks exhibit considerable performance gains even at lower SNR values compared to 8PSK‐turbo trellis coded modulation (TTCM). The simulation results of the proposed scheme have up to 5.5 dB coding gain compared to 8PSK‐TTCM for all cases. It is interesting that after a constant SNR value, 2L‐TC with blind equalizer has better error performance than non‐blind filtered schemes. We conclude that our proposed scheme has promising results compared to classical schemes for all SNR values in WSSUS channels. Copyright © 2005 John Wiley & Sons, Ltd.     

A Memory‐Efficient Block‐wise MAP Decoder Architecture

Next generation mobile communication system, such as IMT‐2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block‐wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit‐error rate (BER) performance of the block‐wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block‐wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.     

Near‐Optimum Blind Decision Feedback Equalization for ATSC Digital Television Receivers

This paper presents a near‐optimum blind decision feedback equalizer (DFE) for the receivers of Advanced Television Systems Committee (ATSC) digital television. By adopting a modified trellis decoder (MTD) with a trace‐ back depth of 1 for the decision device in the DFE, we obtain a hardware‐efficient, blind DFE approaching the performance of an optimum DFE which has no error propagation. In the MTD, the absolute distance is used rather than the squared Euclidean distance for the computation of the branch metrics. This results in a reduction of the computational complexity over the original trellis decoding scheme. Compared to the conventional slicer, the MTD shows an outstanding performance improvement in decision error probability and is comparable to the original trellis decoder using the Euclidean distance. Reducing error propagation by use of the MTD in the DFE leads to the improvement of convergence performance in terms of convergence speed and residual error. Simulation results show that the proposed blind DFE performs much better than the blind DFE with the slicer, and the difference is prominent at the trellis decoder following the blind DFE.     

A Novel Parallel Viterbi Decoding Scheme for NoC‐Based Software‐Defined Radio System

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software‐defined radio (SDR) system. It implements a divide‐and‐conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network‐on‐chip‐based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state‐of‐the‐art methods.     

Trellis‐Based Decoding of High‐Dimensional Block Turbo Codes

This paper introduces an efficient iterative decoding method for high‐dimensional block turbo codes. To improve the decoding performance, we modified the soft decision Viterbi decoding algorithm, which is a trellis‐based method. The iteration number can be significantly reduced in the soft output decoding process by applying multiple usage of extrinsic reliability information from all available axes and appropriately normalizing them. Our simulation results reveal that the proposed decoding process needs only about 30% of the iterations required to obtain the same performance with the conventional method at a bit error rate range of 10^?5 to 10^?6.     

Iterative threshold decoding without interleaving for convolutional self-doubly orthogonal codes

A novel iterative error control technique based on the threshold decoding algorithm and new convolutional self-doubly orthogonal codes is proposed. It differs from parallel concatenated turbo decoding as it uses a single convolutional encoder, a single decoder and hence no interleaver, neither at encoding nor at decoding. Decoding is performed iteratively using a single threshold decoder at each iteration, thereby providing good tradeoff between complexity, latency and error performance.     

A Two‐Stage Radix‐4 Viterbi Decoder for Multiband OFDM UWB Systems

This letter presents a power efficient 64‐state Viterbi decoder (VD) employing a two‐stage radix‐4 add‐compare‐select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared. Implementation results show that the proposed VD architecture is suitable for multiband orthogonal frequency‐division multiplexing (MB‐OFDM) ultra‐wideband (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18‐μm CMOS technology.     

Semi-Iterative Analog Turbo Decoding

Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performance. The proposed algorithm and architecture are applied to design an analog decoder for double-binary codes. Taking full advantage of multiple slice codes, the on-chip area is shown to be reduced by ten when compared to a conventional fully parallelized analog slice turbo decoder. The reconfigurable analog core area for frames of 40 bits up to 2432 bits is 37 nm² in a 0.25-mum BiCMOS process.     

Operation reduced low‐density parity‐check decoding algorithms for low power communication systems

Decoding operation reduction algorithms on min‐sum layered low‐density parity‐check (LDPC) decoders are proposed in this paper. Our algorithm freezes selected operations in high reliable nodes to reduce power while preserving error correcting performance. Both memory accesses and active node switching activities can be reduced. A novel node refresh mechanism reactivates frozen nodes to minimize coding gain degradation. We propose three decoding operation reduction algorithm variations to trade‐off complexity and operation reduction for LDPC decoders with different degrees of parallelism and memory requirement. Simulation results show that the number of LDPC decoding operations is reduced across all SNR ranges. The decoding convergence speed is not affected. Hardware architecture and FPGA implementation for IEEE 802.16e LDPC codes are presented. Copyright © 2011 John Wiley & Sons, Ltd.     

Low‐complexity turbo detection for single‐carrier low‐density parity‐check‐coded multiple‐input multiple‐output underwater acoustic communications

A low‐complexity turbo detection scheme is proposed for single‐carrier multiple‐input multiple‐output (MIMO) underwater acoustic (UWA) communications using low‐density parity‐check (LDPC) channel coding. The low complexity of the proposed detection algorithm is achieved in two aspects: first, the frequency‐domain equalization technique is adopted, and it maintains a low complexity irrespective of the highly dispersive UWA channels; second, the computation of the soft equalizer output, in the form of extrinsic log‐likelihood ratio, is performed with an approximating method, which further reduces the complexity. Moreover, attributed to the LDPC decoding, the turbo detection converges within only a few iterations. The proposed turbo detection scheme has been used for processing real‐world data collected in two different undersea trials: WHOI09 and ACOMM09. Experimental results show that it provides robust detection for MIMO UWA communications with different modulations and different symbol rates, at different transmission ranges. Copyright © 2011 John Wiley & Sons, Ltd.     

A simple soft linear detection for coded multi‐input multi‐output systems

We propose a very simple and efficient soft linear multi‐input multi‐output (MIMO) detection scheme. The detection process is divided into two separate problems. The proposed scheme first detects MIMO symbols using conventional linear detection methods and produces soft bit information using a simple soft demapping method. Next, we refine the soft information by accounting for uneven post‐detection noise variance across MIMO layers. From the simulation result investigated in this paper, we first emphasize that powerful channel coding may suppress the differences of diversity gains among various MIMO detection schemes. This implies that the channel decoding operation may not be transparent to performance gain that resulted from MIMO detection process. The proposed scheme concentrates on accurate estimation of soft post‐MIMO detected information in a very simple manner, rather than concentrating on a complex MIMO detection scheme prior to decoding process. In combination with turbo codes, the proposed scheme produces comparable performance to maximum likelihood detection, even with the simplest scheme such as zero forcing detection, with drastically reduced complexity. Copyright © 2011 John Wiley & Sons, Ltd.     

A Low Complexity Decoding Algorithm for Extended Turbo Product Codes

In this letter, we propose a low complexity algorithm for extended turbo product codes by considering both the encoding and decoding aspects. For the encoding part, a new encoding scheme is presented for which the operations of looking up and fetching error patterns are no longer necessary, and thus the lookup table can be omitted. For the decoder, a new algorithm is proposed to extract the extrinsic information and reduce the redundancy. This new algorithm can reduce decoding complexity greatly and enhance the performance of the decoder. Simulation results are presented to show the effectiveness of the proposed scheme.     

Performance of joint multilevel/AES‐LDPCC‐CPFSK schemes over wireless sensor networks

In wireless sensor networks, data encryption and channel coding are considered together for ensuring secure and robust communication. In order to achieve this purpose, we introduce a new joint scheme, namely ‘Multilevel/Advanced Encryption Standard‐Low Density Parity Check Coded‐Continuous Phase Frequency Shift Keying (ML/AES‐LDPCC‐CPFSK)’. AES algorithm is the most powerful and widely used symmetric key cryptography in providing secure data transmission. LDPC codes have very large Euclidean distance and use iterative decoding algorithms. In this study, we have increased error performance employing multilevel structure to AES and LDPC. In all communications systems, phase discontinuities of modulated signals result in extra bandwidth requirements. CPFSK, which is a special type of continuous phase modulation, is a powerful solution for this problem. In this paper, we simulate error performance of ML/AES‐LDPCC‐CPFSK for regular LDPC codes. Simulation results are drawn for 4CPFSK, 8CPFSK and 16CPFSK over wireless cooperative sensor networks. Using this scheme, we are able to improve bit error performance, channel throughput, security level of communication and reduction in complexity compared with related schemes such as various turbo code structures. Copyright © 2009 John Wiley & Sons, Ltd.     

Low-power log-MAP decoding based on reduced metric memory access

Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards such as W-CDMA and CDMA2000. Although several low-power techniques have been proposed, power consumption is still a major issue to be solved in practical implementations. Since turbo decoding is classified as a memory-intensive algorithm, reducing memory accesses is crucial to achieve a low power design. To reduce the number of memory accesses for maximum a posteriori (MAP) decoding, this paper proposes an approximate reverse calculation method that can be implemented with simple arithmetic operations such as addition and comparison. Simulation results show that the proposed method applied to the W-CDMA standard reduces the access rate of the backward metric memory by 87% without degrading error-correcting performance. A prototype log-MAP decoder based on the proposed reverse calculation achieves 29% power reduction compared to a conventional decoder that does not use the reverse calculation.     

Efficient SIC-MMSE MIMO detection with three iterative loops

In this paper, we propose an efficient joint iterative detection and decoding (JIDD) scheme with a soft interference cancellation minimum mean squared error (SIC-MMSE) based method for a turbo coded multiple-input multiple-output (MIMO) system. In the proposed method, we activate a loop inside the SIC-MMSE based MIMO detection process in addition to the iterative loop between the MIMO detector and turbo decoder, so that the iteration inside the SIC-MMSE detection can be performed in parallel to the iterations inside the turbo decoder. Subsequently, soft outputs from each loop is exchanged for next further iteration, and this makes three iterative loops in total. In comparison with the conventional JIDD schemes, employing additional loop inside the MIMO detection process largely contributes to enhance the performance. In addition, the additional loop speeds up the performance convergence and eventually requires smaller overall computational complexity at the same performance.     

Fast turbo codes with space‐time block codes in fast fading channels

In this paper, space‐time block coding has been used in conjunction with Turbo codes to provide good diversity and coding gains. A new method of dividing turbo encoder and decoder into several parallel encoding and decoding blocks is considered. These blocks work simultaneously and yield a faster coding scheme in comparison to classical Turbo codes. The system concatenates fast Turbo coding as an outer code with Alamouti's G2 space‐time block coding scheme as an inner code, achieving benefits associated with both techniques including acceptable diversity and coding gain as well as short coding delay. In this paper, fast fading Rayleigh and Rician channels are considered for discussion. For Rayleigh fading channels, a fixed frame size and channel memory length of 5000 and 10, respectively, the coding gain is 7.5 dB and bit error rate (BER) of 10^?4 is achieved at 7 dB. For the same frame size and channel memory length, Rician fading channel yields the same BER at about 4.5 dB. Copyright © 2013 John Wiley & Sons, Ltd.     

EM‐based iterative receiver for coded MIMO systems in unknown spatially correlated noise

We present iterative channel estimation and decoding schemes for multi‐input multi‐output (MIMO) Rayleigh block fading channels in spatially correlated noise. An expectation‐maximization (EM) algorithm is utilized to find the maximum likelihood (ML) estimates of the channel and spatial noise covariance matrices, and to compute soft information of coded symbols which is sent to an error‐control decoder. The extrinsic information produced by the decoder is then used to refine channel estimation. Several iterations are performed between the above channel estimation and decoding steps. We derive modified Cramer–Rao Bound (MCRB) for the unknown channel and noise parameters, and show that the proposed EM‐based channel estimation scheme achieves the MCRB at medium and high SNRs. For a bit error rate of 10⁻⁶ and long frame length, there is negligible performance difference between the proposed scheme and the ideal coherent detector that utilizes the true channel and noise covariance matrices. Copyright © 2006 John Wiley & Sons, Ltd.