Inductor implementation using a canonical number of active and passive elements

There is quite a large number of active simulated inductor realizations in the literature, but all of these presented topologies except the recently proposed inductor simulators have either more than one active component or more than a minimum number of passive components. Two resistors and one capacitor are the required canonical number of passive elements to implement a simulated inductor. In this study, a new topology using a single minus-type modified inverting first-generation current conveyor (MICCI-) as a novel active device and a minimum number of passive elements is proposed. The MICCI- is a voltage gain-variable current conveyor (GVCC). Simulation results and non-ideal voltage and current gains effects for the proposed circuit are given.     

A Novel Hybrid Active Inductor

In this brief, a novel hybrid inductor is proposed. The circuit is a hybrid of an operational amplifier and a current conveyor with three passive elements, and offers advantages over conventional current conveyor implementations in its ability to produce high quality factor inductors. Experimental and PSPICE simulation results are presented which verify the theoretical derivations.     

Canonical inductor simulators with grounded capacitors using DCCII

Differential current conveyor (DCCII) can be defined as a second-generation current conveyor with current differencing capability. In this article, a BJT implementation of the DCCII is introduced. Also, to emphasise the advantage of this active element, two new inductance simulator circuits are proposed as application examples. Furthermore, the presented inductor simulator circuits employ a minimum number of elements and they enjoy having grounded capacitors. Experimental and simulation results are given to verify theoretical analyses.     

New active-gyrator circuit using a single current conveyer

A new canonic active RC circuit for realizing an ideal grounded inductor using a single second generation current conveyor as the active building block is described. The circuit may be considered as a novel active-gyrator circuit realized using only a single current conveyor.     

基于E型频变负阻的五阶椭圆高通滤波器设计

用电流传送器实现的E型频变负阻、接地电感和浮地电感作为单元电路,提出了实现高阶椭圆高通滤波器的设计方法.用该方法设计的有源滤波电路具有无源梯形网络原型的低灵敏度特性,给出了五阶椭圆高通滤波器的设计例子和PSPICE仿真结果.     

An Improved Chua's Circuit and Its Use in Hyperchaotic Circuit

An improved implementation of Chua's circuit using dual output current conveyor is presented. The present proposal offers the advantages of low component count, current mode processing, availability of current across inductor and availability of voltage across inductor in form of current. The application of present circuit in designing low hardware inductorless hyperchaotic circuit is also presented. The paper concludes with a discussion of advantages of present proposal of Chua's circuit and inductorless hyper chaotic circuit thus designed over their earlier counterparts. The designs are adequately supported by SPICE simulation results. Patent pending.     

On the Realization of Simulated Inductors with Reduced Parasitic Impedance Effects

In this paper, a method for reducing the parasitic impedance effects of the current feedback operational amplifiers (CFOAs) in an inductor simulator at low frequencies is proposed. Also, two novel grounded inductors employing a current follower (CF) and a second generation current conveyor (CCII) are given to illustrate the parasitic reduction technique clearly. The low frequency restrictions of the proposed inductors due to terminal parasitic resistances can be improved by using the presented parasitic impedance reduction technique. SPICE simulations show that the presented inductor employing CFOAs in a voltage-mode (VM) band-pass and high-pass filter application has lower parasitic effects at low frequencies. In addition to simulation results, experimental test results are given to verify the theory.     

CCC Ⅱ模拟电感的非理想特性分析及应用

提出了利用理想第二代电流控制传输器(CCC II)模拟电感特性的结构。分析了基于CCC II模拟电感的理想电感效应有效范围、主要寄生电容电阻的影响及其补偿方法,给出了模拟电感特性仿真结果。在此基础上,对5阶巴特沃斯(Butterworth)高通滤波器进行综合。电路具有结构简单、集成度高,截止频率连续可调等优点。仿真结果证明了设计的正确性。     

Novel CMOS realizations of the inverting second-generation current conveyor and applications

This paper presents two new CMOS realizations for the inverting current conveyor (ICCII). The proposed realizations offer enhanced features compared to previously reported ICCII. Also new oscillator circuits based on using the ICCII as an active element are presented. The presented oscillator circuits have the advantage that both the oscillation frequency and the oscillation condition can be adjusted independently. Also another application to the ICCII, which is a floating inductor, is proposed. A second order low pass filter using the proposed floating inductor is simulated and compared with the ideal result. The proposed ICCIIs and the presented applications are tested with SPICE simulations using CMOS 0.35 μm technology to verify the theoretical results.     

Inverting voltage buffer based lossless grounded inductor simulators

In this study, two new lossless grounded inductor simulators (GISs) made up of a single plus-type second-generation current conveyor, two inverting voltage buffers and a minimum number of passive components are proposed. There is no requirement of matching conditions and cancellation constraints among passive elements of the proposed GISs. Nevertheless, both of the proposed GISs have a floating capacitor which can be easily realized in nowadays integrated circuit fabrication. A second-order voltage-mode band-pass filter application is given for the proposed lossless GISs. A number of simulations based on SPICE program are given so as to verify the theory.     

电流模集成电抗元件与频率变换电路的设计

为了拓宽电流模单元电路结构在低压低功耗射频集成电路中的应用,研究把第二代电流传输器用作电抗器件和频率变换电路。以第二代电流传输器为核心,辅助予外围电路,构造从输入到输出端口不同性质传输阻抗的有源电容倍增器和有源电感,并且基于第二代电流传输器组合结构差异的分析,设计了集成频率变换电路。从理论上,推出有源电容倍增器和有源电感结构的合理性。仿真集成频率变换电路,结果袁明对40MHz以下正弦波倍频功能正确,且以100kHz正弦波为调制信号和以10MHz的正弦波为载波获得了双边带调幅信号。这为射频集成电路设计提供了新的思路。     

Synthesis of active inductors using SFG stamps

This paper proposes a new approach for the systematic synthesis of active inductors via signal-flow graphs (SFGs). The basic idea consists of proposing and using SFG stamps of active basic building blocks (ABBs) to construct the equivalent SFG of a classical inductor. We show that a large number of active inductors can be thus synthesized; twelve are proposed, most of them are novel. Known ABBs, as well as newly proposed ones are used, namely current conveyors (CC), operational transconductance amplifiers (OTA), current conveyor transconductance amplifiers (CCII-TA), current feedback operational amplifiers (CFOA), operational transresistance amplifiers (OTRA), current backward transconductance amplifiers (CBTA), current feedback transconductance amplifiers (CFTA) and voltage differencing inverting buffered amplifiers (VDIBA). SPICE simulations are given to show the viability of the proposed technique.     

Floating Immittance Function Simulator and Its Applications

A new floating immittance function simulator circuit is proposed using two different active elements, a dual-output second generation current conveyor (DO-CCII) and an operational transconductance amplifier (OTA). The presented circuit can realize a positive and negative floating inductor, capacitor and resistor depending on the passive component selection. Since the passive elements are all grounded, this circuit is suitable for fully integrated circuit design. The circuit does not require any component matching conditions, and it has a good sensitivity performance with respect to tracking errors. Moreover, the proposed positive and negative inductance, capacitor and resistor simulator can be tuned electronically by changing the biasing current of the OTA or can be controlled through the grounded resistor or capacitor. The proposed floating inductor simulator circuit is demonstrated by using a SPICE simulation for 0.35 μm TSMC CMOS technology. The proposed circuit consumes an average power of 1 mW using ±1.5 V supply voltages.     

Systematic synthesis of R-L and C-D immittances using single CCIII

We present a systematic approach to the synthesis of R–L (resistor–inductor) and C–D (capacitor–frequency-dependent negative resistance) configurations by using a single third-generation current conveyor (CCIII) and a minimum number of passive elements. All the simulated immittance values can be orthogonally adjusted, there are no requirements for any certain element matching or cancellation constraints. The test filter circuits, constructed with the derived R–L immittances, are used to verify the theory by HSPICE simulations. The simulation results corroborating all our theoretical predictions are incorporated in the work. This methodology can be extended to the immittance synthesis based on different active elements.     

含全耦合电感电路的求解

分析动态电路既可以应用拉普拉斯变换方法,也可采用时域分析方法。通过分析含全耦合电感电路,得出流入耦合电感的电流有可能发生跃变的结论,该电流不是电路的状态变量。对含全耦合电感电路的求解以拉普拉斯变换方法为宜。如果采用时域分析方法,则应采用含全耦合电感电路的等效电路来求解。上述分析结果可供讲授电路理论的教师参考。     

New Fully‐Differential CMOS Second‐Generation Current Conveyer

This paper presents a new CMOS fully‐differential second‐generation current conveyor (FDCCII). The proposed FDCCII is based on a fully‐differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit operating at a supply voltage of ± 1.5 V, it has a total standby current of 380 µA. The applications of the FDCCII to realize a variable gain amplifier, fully‐differential integrator, and fully‐differential second‐order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 µm technology.     

Quadrature Oscillators with Grounded Capacitors and Resistors Using FDCCIIs

Two current‐mode and/or voltage‐mode quadrature oscillator circuits each using one fully‐differential second‐generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current‐mode quadrature signals have the advantage of high‐output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current‐mode and voltage‐mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.     

A Buck-Derived Topology With Improved Step-Down Transient Performance

The slew rate of the inductor current is limited by the inductance value and the voltage across the inductor. In a buck converter, when the controller is saturated, the voltage across the inductor during a step-up load transient is $V_{rm in}-V_{rm out}$, while during a step-down load transient, it is $-V_{rm out}$. Thus, a buck converter with a large conversion ratio offers asymmetrical step-up and step-down transients. Since the rate of fall of the inductor current is much slower than the rate of rise of the inductor current, the step-down transient lasts longer than the step-up transient for the same change in the load current. The step-down slew rate can be increased by reducing the inductance, but it results in higher inductor current ripple, and hence, higher losses in the power converters. In this paper, we present a novel topology for improving the step-down load transients without reducing the inductance value. The scheme operates only during load transients and restores to the normal operating conditions during steady-state operation. It provides reduced voltage overshoots and faster settling times in output voltage during such transients. The proposed scheme is tested on a 1-V/12-A buck converter switching at 1 MHz, and the experimental results are presented.      

Design of Components and Circuits Underneath Integrated Inductors

In this paper, we present a study of the eddy current effect of devices placed underneath and inside an on-chip inductor. We verified the performance of such area-saving structures through electromagnetic (EM) simulations and measurement of test structures. We used layout techniques to minimize eddy current loss and magnetic coupling between the devices and the inductor, and constructed a complete voltage-controlled oscillator (VCO) inside an inductor. Measurement results show that this compact VCO has an equal performance in phase noise and output power as compared to a traditional VCO while reducing the area by about 50%. The techniques presented in this paper are general and can be implemented in most layouts without extra post-processing steps.     

Analysis of the Noise Characteristics of CMOS Current Conveyors

The definition of the current conveyor is reviewed and a multiple-output second generation current conveyor (CCII) is shown to combine the different generations of current conveyors presently existing. Next, noise sources are introduced, and a general noise model for the current conveyor is described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches to an optimization of the noise performance are discussed. It is concluded that a class AB implementation can yield a lower noise output for the same dynamic range than a class A implementation. For both the class A implementation and the class AB implementation it is essential to design low noise current mirrors and current sources, and with the class AB design, the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current.