In_(0.5)Ga_(0.5)P/GaAs二维空穴气p沟异质结场效应管

提出了一种新颖的 Ga As基 p沟异质结场效应管 (p HFET)概念 ,器件采用了 In0 .5Ga0 .5P/ Ga As异质系统及二维空穴气 (2 DHG)原理以改善 Ga As的空穴输运特性。据此原理研制的器件可在室温下工作 ,其实验结果为 :室温下 ,饱和电流 Idss=6 1m A/ mm,跨导 gm=4 1m S/ mm;77K下 ,饱和电流 Idss=94 m A/ mm,跨导 gm=6 1m S/ mm。预计该器件在微波和数字电路中极佳的电流密度及高频增益 ,因而具有良好的应用潜力。     

A high fill factor and progressive scan PtSi Schottky-barrier IR-CCD image sensor using new wiring technology

A back surface illuminated 130/spl times/130 pixel PtSi Schottky-barrier (SB) IR-CCD image sensor has been developed by using new wiring technology, referred to as CLOSE Wiring, CLOSE Wiring, designed to effectively utilize the space over the SB photodiodes, brings about flexibility in clock line designing, high fill factor, and large charge handling capability in a vertical CCD (VCCD). This image sensor uses a progressive scanned interline-scheme, and has a 64.4% fill factor in a 30 /spl mu/m/spl times/30 /spl mu/m pixel, a 3.9 mm/spl times/3.9 mm image area, and a 5.5 mm/spl times/5.5 mm chip size. The charge handling capability for the 3.3 /spl mu/m wide VCCD achieves 9.8/spl times/10/sup 5/ electrons, The noise equivalent temperature difference obtained was 0.099 K for operation at 120 frames/sec with a 50 mm f/1.3 lens.<>     

1 W/mm RF power density at 3.2 GHz for a dual-layer RESURF LDMOStransistor

In this letter, we present state-of-the-art performance, in terms of output power density, for an RF-power LDMOS transistor. The novel device structure has a dual-layer RESURF of the drift region, which allows for a sub-μm channel length and a high breakdown voltage of 110 V. The output power density is more than 2 W/mm at 1 GHz and a V_DS=70 V, with a stable gain of 23 dB at V_DS=50 V. At 3.2 GHz the power density is over 1 W/mm at V_DS=50 V and 0.6 W/mm at V_DS=28 V. These results are to our knowledge the best ever for silicon power MOSFETs     

A 65 nm 2-Billion Transistor Quad-Core Itanium Processor

This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s.     

A 16 bit/spl times/16 bit pipelined multiplier macrocell

A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfiguration of the basic array can be performed. The multiplier macrocell measures 1.7 mm/spl times/1.7 mm.     

Miniaturisation of microstrip patch antenna using perturbation of radiating slot

A highly miniaturised rectangular microstrip patch antenna using deformation of the patch structure has been designed and fabricated at a frequency of 1.575 GHz (GPS). The fabricated antenna has a patch with an overall rectangular shape and depressed at its four corners (corner depressed microstrip patch antenna, CDMPA). In the linear polarisation, at a fixed rate of 1.2 of width/length (W/L), the CDMPA (53/spl times/63.6 mm) is reduced to 43.9% of the general plane type microstrip patch antenna (MPA, 80/spl times/96 mm) in patch size. The gain is 4.3 dBd which is lower than that of the general MPA (8 dBd) by 3.7 dB. In the circular polarisation, the patch size of the CDMPA (54.2/spl times/61.5 mm) is reduced to 52.8% of that of the MPA (76/spl times/83 mm). The axial ratio (AR) and axial ratio band width (ARBW) within 2 dB are 1.5 dB and 20 MHz (1.27%), respectively. The gain is 2.5 dBd, which is lower than that (4.2 dBd) of the general MPA by 1.7 dB.     

Metamorphic InAlAs/InGaAs enhancement mode HEMTs on GaAs substrates

In_0.5Al_0.5As/In_0.5Ga_0.5 As HEMTs have been grown metamorphically on GaAs substrates oriented 6° off (100) toward (111)A using a graded InAlAs buffer. The devices are enhancement mode and show good dc and RF performance. The 0.6-μm gate length devices have saturation currents of 262 mA/mm at a gate bias of 0.7 V and a peak transconductance of 647 mS/mm. The 0.6 μm×3 mm devices tested on-wafer have output powers up to 30 mW/mm and 46% power-added-efficiency (PAE) at 1 V drain bias and 850 MHz. When biased and matched for best efficiency performance, this same device has up to 68% PAE at V_d=1 V     

Diamond surface-channel FET structure with 200 V breakdown voltage

An enhancement mode diamond FET using a hydrogen-terminated surface as hole conductive channel has been fabricated with 200 V gate to drain breakdown voltage. At the 8.5-μm gate length the maximum drain current was 22 mA/mm. 90 mA/mm maximum drain current was obtained at a gate length of 3.0 μm. Scaling to below 1 μm gate length assuming undegraded breakdown conditions will result in a projected RF power handling capability above 6 W/mm     

Low-voltage operation of the retarding-field oscillator at X band and in the millimeter wavelength region

This paper concerns the partial development of two low-voltage designs of the retarding-field oscillator. These designs differ fundamentally in their power coupling system. TheX-band model has coaxial-line coupling to a waveguide while the millimeter wavelength model has double-cavity coupling to a waveguide. The design developed atXband allows operation with the anode voltage as low as 200 volts and as high as 600 volts. Radio-frequency output power of 20 milliwatts at 200 volts and better than 1 watt at 600 volts is possible. In the millimeter wavelength range, three double-cavity designs have been investigated. These tubes operate in the range of from 4.30 to 5.20 mm, 5.00 to 6.4 mm, and 5.80 to 6.8 mm, respectively. All of these oscillators have anode potentials of 800 volts or less. An output power of 175 milliwatts has been obtained at a wavelength of 6.00 mm. A digest of characteristics possessed by important models of the retarding-field oscillator investigated as of November, 1957, also is included.     

An all implanted self-aligned enhancement mode n-JFET with Zn gatesfor GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p⁺ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 μm JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p⁺/n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f_t of 19 GHz with an f_max of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits     

A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's

We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-Å) n-channel implant, an n⁺source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-Å) abrupt p-n junction, followed by a rapid thermal activation. From FET's with gates 2 µm long, a transconductance of 50 mS/mm and an output impedance of 400 Ω.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at Vgs= 0 V with negligible drift.     

Quantum-well-doped FET (QUD-FET)

A novel FET using a 2DEG is presented. The FET has an AlAs/GaAs/AlAs single quantum well with planar doping in the centre of the GaAs layer. The conduction channels are composed of a 2DEG generated in undoped GaAs layers outside the well. The measured 2DEG concentration was 1.8?2 × 1012cm?2 with electron mobilities of 3500cm2/Vs at RT and 10500cm2/Vs at 77K. A 1.5?m-gate-length FET exhibits a maximum transconductance of 174 mS/mm and a maximum current exceeding 300 mA/mm at 77K.     

蓝宝石衬底上Ka波段AlN/GaN高电子迁移率晶体管

We report the DC and RF characteristics of AlN/GaN high electron mobility transistors(HEMTs) with the gate length of 100 nm on sapphire substrates. The device exhibits a maximum drain current density of 1.29 A/mm and a peak transconductance of 440 m S/mm. A current gain cutoff frequency and a maximum oscillation frequency of 119 GHz and 155 GHz have been obtained, respectively. Furthermore, the large signal load pull characteristics of the AlN/GaN HEMTs were measured at 29 GHz. An output power density of 429 m W/mm has been demonstrated at a drain bias of 10 V. To the authors’ best knowledge, this is the earliest demonstration of power density at the Ka band for Al N/Ga N HEMTs in the domestic, and also a high frequency of load-pull measurements for Al N/Ga N HEMTs.     

Integrated acoustooptic modules for interferometric RF spectrum analyzers

An integrated acoustooptic (AO) module that consists of a wideband AO Bragg cell, a wide-angle ion-milled concave Bragg grating lens, and a large-aperture titanium-indiffusion proton-exchange lens has been realized in a y-cut LiNbO/sub 3/ waveguide 1*8*16 mm/sup 3/ in size and used to perform interferometric RF spectrum analysis. This module has provided a bandwidth of 205 MHz centered at 350 MHz and single-tone instantaneous and two-tone, third-order spurious-free dynamic ranges of 50 and 40 dB, respectively, at 1.0 mW of 0.6328- mu m laser power and a drive power of 50 mW per RF signal. A pair of such basic AO modules has been integrated in a common LiNbO/sub 3/ substrate 1*10*16 mm/sup 3/ in size to facilitate measurement of the phase difference, and thus the angle of arrival, of RF signals.<>     

A high-speed high-density silicon 8/spl times/8-bit parallel multiplier

An 8/spl times/8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61/spl times/0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.     

High-performance GaAs power MESFET with AlGaAs buffer layer

The performance of a power MESFET has been significantly improved by using an AlGaAs heterobuffer. The conduction-band discontinuity at the heterointerface acts as a potential barrier for electron confinement; the RF conversion efficiency and power gain of the FET were very high compared with a standard MESFET. We have achieved 41% power-added efficiency with 0.88 W/mm power density at 21.5 GHz and 30% efficiency with 0.56 W/mm at 35 GHz.     

中波红外三视场变焦光学系统设计

三视场变焦光学系统相对于其他形式的变焦系统具有机械结构简单、可靠性高、变焦时间短等优点。采用320240分辨率、像元尺寸30 m30 m制冷型探测器,二次成像方式设计了一种工作于3～5 m中波制冷型三视场红外光学系统,系统视场角1.4～23.8,F数为４,可实现焦距为30mm/100mm/500mm。设计中采用了硅和锗两种材料校正谱段内色差,采用了一个非球面校正系统球差,两个反射镜折转光路的方式实现系统轴向尺寸的缩减,整个系统外形尺寸小于210 mm160 mm120 mm,系统具有外形尺寸小、变焦结构简单、成像质量高等特点,在空间频率17 lp/mm处,系统调制传递函数（MTF）均在0.5以上,能量集中度大于70%。     

Ga_(1-x)Al_xAs/GaAs异质结构二维电子气晶体管(TEGFET)

制备了耗尽型和增强型TEGFET,耗尽TEGFE单栅长1μm,其室温跨导g_m=90mS/mm;双栅栅长均为2μm。g_m=75mS/mm。双栅的结果优于本实验室相同结构与尺寸的离子注入型常规双栅MESFET与高掺杂沟道MIS结构肖特基势垒FET的实验结果。双栅耗尽型器件在77K下跨导增加到1.7倍。双栅增强型的TEGFET在室温0.6V栅偏压下,g_m=63mS/mm,在77K下增加到1.4倍。如器件中出现平行电导时,则器件性能退化,它不但使跨导降低,且随栅编压变化很大。文中讨论了这一现象。     

An interdigital bandpass filter embedded in LTCC for 5-GHz wireless LAN applications

This letter presents a compact interdigital stripline bandpass filter embedded in low temperature cofired ceramic for 5-GHz wireless LAN applications, including design, simulation, fabrication, and measurements. The filter measures 8 mm/spl times/7 mm/spl times/1.1 mm and exhibits an insertion loss of 3.6 dB, a return loss of 20 dB, and a 212-MHz passband with the midband frequency at 5.28 GHz. The filter is highly reproducible with good tolerance. A low noise amplifier (LNA) built on the top of the LTCC substrate with an embedded filter has the same bandwidth and midband frequency as those of the filter. Using this filter and an integrated chip, a small RF front-end receiver has been achieved.     

真空平板玻璃激光封接气孔控制研究

为了探究激光焊接真空平板玻璃封接层气孔的产生机理，利用扫描电镜、自带能谱仪、X射线衍射仪和金相显微镜等手段，进行了真空平板玻璃激光侧边封接试验，研究了激光功率和焊接速率对封接层气孔的影响，分析气孔产生的原因。结果表明, 真空平板玻璃封接层出现了数量较多、大小不一、相互不连通的孤立气孔，位于颗粒的交界处，主要是由焊料颗粒间的残余空气引起的; 在焊接速率为2mm/s和离焦量为-2mm的条件下，过低或过高的激光功率都不利于减少封接层的气孔缺陷，激光功率为80W(能量密度为80J/mm2)时，封接层组织形貌好，封接层封接质量佳; 在激光功率为80W和离焦量为-2mm的条件下，较低的焊接速率将有利于减少封接层的气孔缺陷，焊接速率为1mm/s(能量密度为160J/mm2)时，封接层组织形貌好，封接层封接质量佳。此研究可为真空平板玻璃的激光封接制造提供理论依据。