Performance and reliability improvement of flash device by a novel programming method

The operating methods of flash memory device are worth studying due to the reliability issue. A novel programming method based on a new current mechanism is developed in this work to improve the performance and reliability of flash memory. Experimental results show that this novel programming method with higher gate current injection efficiency not only increases the operating speed but also improves the reliability. This reliability improvement can be attributed to the reduction of oxide-trap-charge generation and threshold-voltage shift.     

6G移动网络中闪存系统的性能优化方案:比特重映射

第6代移动通信技术(6G)网络所产生的海量数据对数据存储带来了全新挑战,推动着存储技术的迅猛发展。与非门(NAND)闪存存储器具有读写速度快,可靠性高等优点,故在6G网络中具有广泛的应用前景。为了提高NAND闪存的可靠性,针对两种不同位线结构的错误特性,该文分别提出基于全位线结构的等精度重映射方案和基于奇偶位线结构的不等精度的重映射方案。仿真结果表明,两种新型比特重映射方案有效提升了闪存的误码性能。基于此,该文所提重映射技术可被视作6G网络中可靠而高效的存储优化技术。     

栅侧壁隔离层对45nm NOR闪存栅极干扰的影响

为了研究侧壁隔离层对闪存器件可靠性的影响,分别制备了Si3N4和SiO2-Si3N4-SiO2-Si3N4 (ONON)复合层作为栅侧壁隔离层的45 nm或非闪存(NOR flash)器件,对编程后、循环擦写后的闪存器进行栅极干扰的测试,讨论了不同栅侧壁隔离层对栅极干扰的影响.结果表明,虽然纯氧化硅隔离层可减少NOR自对准接触孔(SAC)刻蚀时对侧壁隔离层的损伤,但其在栅极干扰时在氧化物-氮化物-氧化物(ONO)处有更高的电场,从而在栅干扰后阈值电压变化较大,且由于在擦写操作过程中会陷入电荷,这些电荷在大的栅极电压和长时间的栅干扰作用下均会对闪存器的可靠性产生负面的影响.ONON隔离层的闪存器无可靠性失效.因此以ONON作为侧壁隔离层比以纯氮化硅作为侧壁隔离层的闪存器件具有更好的栅干扰性能.     

A system LSI memory redundancy technique using an ie-flash(inverse-gate-electrode flash) programming circuit

A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor     

A new erase method for scaled NAND flash memory device

A suitable bird-beak thickness is crucial to the cell reliability. However, the process control for bird-beak thickness in the edge region is very difficult. A new erase method is proposed in this work to modulate the electron tunneling region of 40 nm floating gate NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3 V/− 0.8 V. The Fowler-Nordheim (FN) current of erase operation distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This new erase method is promising for scaled NAND flash memory.     

A statistical model for SILC in flash memories

The reliability of flash memories is strongly. limited by the stress-induced leakage current (SILC), which leads to accelerated charge-loss phenomena in a few anomalous cells. Estimating the reliability of large flash arrays requires that physically-based models for the statistical distribution of SILC are developed. In this paper, we show a physical model for the leakage mechanism in thin oxides, which is able us to explain the anomalous leakage-conduction in tail cells. The physical model is then used for a quantitative evaluation of the SILC distribution in large flash arrays. The new model can reproduce the statistics of SILC for a wide range of tunnel-oxide thickness, and can provide a straightforward estimation of the reliability for large flash arrays.     

An improved minimizing algorithm for sum of disjoint products[reliability theory]

The Abraham-Locks-revised (ALR) sum-of-disjoint products (SDP) algorithm is an efficient method for obtaining a system reliability formula. The author describes a minor modification of the ALR algorithm called the Abraham-Locks-Wilson (ALW) method. The new feature is an alternative method of ordering paths and terms. ALW obtains a shorter disjoint system formula on a test example than any previous SDP method and allows small computational savings in processing large paths of complex networks. As there are different ways to obtain a reliability formula it is useful to use an approach which yields the smallest formula relative to computational effort expended. The extra effort in ordering the terms should be reasonably small and usually leads to improved efficiency in the later stages of the algorithm. ALW allows the analyst to operate in a more efficient way on many problems, particularly if the overlap ordering is used in the early stages of processing but is probably ignored for terms that contain a majority of the Boolean variables     

Equivalent cell approach for extraction of the SILC distribution inflash EEPROM cells

A new method for characterizing the distribution of the stress-induced leakage current (SILC) in flash memories is presented. The statistics of the leakage parameters are extracted directly from the time dependence of the threshold voltage distributions obtained in a single gate-stress experiment, without any need for tracking the behavior of the individual cells. The new technique can be used for fast evaluation and reliability projections, as well as providing a tool for statistical investigation on the oxide leakage mechanisms     

Relation between robustness against ESD and against flash events in deflection amplifiers

We have investigated the relation between the electrostatic discharge (ESD) level achieved by vertical deflection amplifiers, used for television sets, and other discharge events affecting the reliability. In particular, it is known that the tubes of television sets sometimes produce so called flashes, which may damage the amplifiers. It is generally assumed that good ESD robustness corresponds to robustness against flash. However, we show that improving ESD performance can sometimes be detrimental to robustness against flash. We discuss the mechanism underlying these seemingly conflicting results and describe a method of improving ESD, while simultaneously enhancing flash robustness.     

多传感器动态参数实时采集与存储方法研究

针对现有的数据采集系统无法兼备通道数多、速度快、实时存储的问题,提出一种基于可编程逻辑器件和大容量Flash的多传感器动态参数实时采集与存储方法。该系统以FPGA为主控制器,实现对模数转换芯片的控制与读取时序;转换后添加校验字节,通过双FIFO缓存方式实现和Flash的高效率数据交互;双Flash实现采集数据备份,增加存储可靠性;双Flash之间总线相互独立,提高数据存储速度;最后通过USB接口实现与上位机的高速数据传递。实验证明:该系统的单通道采样速率可达2MHz,实时存储速率单片Flash可达50MByte/s字节,双片可达100MByte/s,在强振动动态测试环境下,能够可靠地采集传感器的输出信号,采集绝对误差在1 mV以内,数据无误码率。满足振动测量的稳定可靠、精度高、抗干扰能力强等要求。     

Quick address detection of anomalous memory cells in a flash memorytest structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test     

低电场应力下闪速存储器的退化特性

基于负栅源边擦除的闪速存储器存储单元,研究了形成应力诱生漏电流的三种导电机制,同时采用新的实验方法对引起瞬态和稳态电流的电压漂移量进行了测量.并利用电容耦合效应模型对闪速存储器存储单元的可靠性进行了研究,结果表明,在低电场应力下,其可靠性问题主要由载流子在氧化层里充放电引起.     

PSpice在高功率固体激光能源系统中的应用

在神光能源系统模块中,依据脉冲氙灯放电特性及氙灯放电回路的技术要求,采用仿真软件OrCAD PSpice分别从脉冲氙灯的五路放电、氙灯能量分配及能源模块在放电过程中存在的故障三个方面进行模拟仿真并给出仿真结果,并与实际装置运行数据进行比较分析,其仿真的结果与实际理论分析结论基本一致,验证了仿真模型及过程的可靠性,这为高功率激光装置的电子计算机辅助设计和分析提供了一种新途径。     

A memory-effective fast algorithm for computing the reliability of complex systems/networks

Boolean reliability analysis of complex technical systems, as well as of technical net-systems (such as telecommunication systems), leads to the problem of computing the terminal pair reliability R^s,t of a netgraph. Among the fastest methods of computing R^s,t is the path method. In enumerates all minimal s−t paths of the net and then makes the paths mutually disjoint. Unfortunately, all paths and all disjoint terms must be available (stored) at the same time. Therefore, the computer memory effort for that method increases exponentially. In contrast, the reliability branching algorithm (RBA) that builds up a branching tree with disjoint tree-nodes (corresponding to the terms of a symbolic reliability expression) is also effective and needs only a low, quadratically increasing memory effort.The present paper gives a new method for symbolic reliability analysis. It is a fusion of the RBA with the path method. We search for one s−t path and compute its reliability. Then we formulate conditions that ensure disjointness for all paths we search on that condition and so on. A condition always reduces the network. The new method combines the advantages of the path method (fast) and the RBA (low memory effort). The algorithm is simple for computation by hand and effective for the use of computers.     

Erratic cell behavior in channel hot electron programming of NOR flash memories

This paper describes for the first time an erratic behavior found in NOR array cells of flash memories after cycling when programming is performed by channel hot electron injection. The effects of different program conditions (i.e., drain and bulk bias, as well as program speed) on such an erratic behavior are discussed and a possible explanation is given. Implications in terms of memory reliability are discussed, in particular for multilevel applications.     

Flash存储器技术与发展

Flash存储器是在20世纪80年代末逐渐发展起来的一种新型半导体不挥发性存储器，它具有结构简单、高密度、低成本、高可靠性和系统的电可擦除性等优点，是当今半导体存储器市场中发展最为迅速的一种存储器。文章对Flash存储器的发展历史和工作机理、单元结构与阵列结构、可靠性、世界发展的现状和未来趋势等进行了深入的探讨。     

A New Algorithm for the Reliability Analysis of Multi-Terminal Networks

In a probabilistic network, source-to-multiple-terminal reliability (SMT reliability) is the probability that a specified vertex can reach every other vertex. This paper derives a new topological formula for the SMT reliability of probabilistic networks. The formula generates only non-cancelling terms. The non-cancelling terms in the reliability expression correspond one-to-one with the acyclic t-subgraphs of the network. An acyclic t-subgraph is an acyclic graph in which every link is in at least one spanning rooted tree of the graph. The sign to be associated with each term is easily computed by counting the vertices and links in the corresponding subgraph. Overall reliability is the probability that every vertex can reach every other vertex in the network. For an undirected network, it is shown the SMT reliability is equal to the overall reliability. The formula is general and applies to networks containing directed or undirected links. Furthermore link failures in the network can be s-dependent. An algorithm is presented for generating all acyclic t-subgraphs and computing the reliability of the network. The reliability expression is obtained in symbolic factored form.     

Statistical profiling of SILC spot in flash memories

A new experimental technique for evaluating the position of the oxide weak spot responsible for the stress-induced leakage current (SILC) in flash memories is presented. The oxide field along the channel is modified by drain biasing, and the gate current is then monitored. The position of the leakage spot can be determined by the shift in the gate current-voltage (I-V) characteristics. Experimental results on flash memory arrays reveal a strong localization of SILC in correspondence of the drain junction, due to the cooperation effects of program/erase (P/E) operations. The technique can be used to optimize the P/E conditions for maximum device reliability.     

An effective approach to improve split-gate flash product data retention

Data retention is one of the most important reliability characteristics of split-gate flash. Therefore, many efforts were made to improve data retention of split-gate flash. By experiments, it was found that higher chlorine concentration produced in FGSP2 oxide deposition can induce worse data retention. Thus, reducing chlorine concentration is an effective approach to improve data retention for split-gate flash product. Additional RTO annealing between FGSP2 oxide deposition and FGSP2 etching could reduce chlorine concentration, and improve FGSP2 oxide film quality, and then get better data retention.     

Unbiased Variance Estimates for System Reliability Estimate Using Block Decompositions

An unbiased estimator is proposed to calculate the variance of a system reliability estimate based on the estimated variance of component reliability estimates. The method does not require any parametric assumptions for component reliability or time-to-failure, and it allows Type-I and Type-II censored data. The approach can be applied to many situations as long as the system can be appropriately decomposed into series or parallel configurations. The new model is compared with existing methods using different reliability data and system structures. The empirical results show that the new model is generally superior in terms of computational efficiency, and estimation accuracy.