Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption     

Low-power design for embedded processors

Minimization of power consumption in portable and battery powered embedded systems has become an important aspect of processor and system design. Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy. A review of low-power techniques applied at many levels of the design hierarchy is presented, and an example of low-power processor architecture is described along with some of the design decisions made in implementation of the architecture     

Low-power design techniques for high-performance CMOS adders

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 μm CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V     

Battery-powered digital CMOS design

In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utilization factor) decreases as the average discharge current from the battery increases. The implication is that the battery life is a superlinear function of the average discharge current. Next we show that even if the average discharge current remains the same, different discharge current profiles (distributions) may result in very different battery lifetimes. In particular, the maximum battery life is achieved when the variance of the discharge current distribution is minimized. Analytical derivations and experimental results underline the importance of the correct modeling of the battery-hardware system as a whole and provide a more accurate basis (i.e., the battery discharge times delay product) for comparing various low-power optimization methodologies and techniques targeted toward battery-powered electronics. Finally, we calculate the optimal value of V/sub dd/ for a battery-powered VLSI circuit so as to minimize the product of the battery discharge times circuit delay.     

数字语音解码器的低功耗设计策略

主要从系统级、算法级、结构级等多个层面综合考虑减少数字语音解码器的功耗.系统级使用双向不交叠时钟技术,在提高耗时长的模块运算频率的同时消除了电路的竞争与冒险;算法级主要使用汇编语言重写和优化原代码,既可以压缩源代码,更能充分挖掘硬件的运算潜力;在结构级,主要利用并行技术,增加协处理器进行并行计算,有效提高运算速度.另外在布局布线时使用全定制集成电路设计技术手工布线,大为减少解码器的芯片面积.     

Low-power design of 8-b embedded CoolRisc microcontroller cores

Low-power and low-voltage embedded microcontrollers are required more and more for portable applications. Power reduction can be addressed at the software level as well as at the architecture level while searching to reduce the number of executed instructions for a given task. An 8-b RISC-like pipelined microcontroller family is presented achieving one clock per instruction. It is compared to various architectures of existing 8-b microcontrollers. According to an efficiency model taking into account the architecture as well as the number of registers, the presented 8-b microcontroller cores provide four to ten times better performances than existing microcontrollers. On one hand, the operating frequency can be reduced to execute a given task in the same execution time. On the other hand, delivering 10 MIPS performance, more than 2000 MIPS/W can be achieved at 3 V     

Low-power CMOS with subvolt supply voltages

We first present a circuit taxonomy along the space and time dimensions, which is useful for classifying generic low-power techniques, followed by an analysis of optimal power supply and threshold voltages and transistor sizing for minimizing the energy-delay product of a class of complementary metal-oxide-semiconductor (CMOS) digital circuits     

Low-power CMOS current conveyor

A novel second-generation CMOS current conveyor based on a new adaptive biasing technique is proposed. It is shown that the use of this circuit offers an excellent performance and leads to a significant reduction in the standby power dissipation. PSPICE simulation results, assuming 0.5 μm CMOS process, are also given     

CIS片上系统中伽玛校正的低功耗设计

为了实现CMOS图像传感器(CIS)片上系统(SoC)中伽玛(γ)校正的低功耗设计,同时又保证校正的精度,提出一种查找表和直线拟合相结合的γ校正技术。算法对灰度值较低的像素使用直接查找表方法校正,对于γ曲线上升缓慢部分的像素采用分段直线拟合的方法。在直线分段时,使用外层分段与内层分段相结合的方法,达到了分段优化的目的。算法保证了图像校正精度,与使用完全查找表法相比,误差在0.5 pixel之内。基于该方法设计了一个8 bit输入/8 bit输出的VLSI模块,通过FPGA对模块进行了验证,模块占用723个LE和195个LC寄存器,比完全查找表法减少了硬件资源耗费,实现了低功耗设计。系统最大工作频率可达148 MHz,完全满足实时处理的需求。     

Low-power CMOS threshold-logic gate

A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

基于CMOS的低功耗基准电路的设计

基于带隙基准的原理,采用0.6μm、N阱CMOS工艺,文章设计了一种工作在亚阈值区的用于锂离子和锂聚合物电池充电保护芯片的低功耗基准电路。Hspice仿真结果表明:基准电压为1.068V,电源电压由1.8V到8V变化,电路最大消耗电流小于0.15μA;温度由-40℃到80℃变化,其温度系数约为±10ppm/℃。整个充电保护芯片测试结果,其功耗小于0.6μW。     

一种具有省电模式CMOS振荡器电路

提出了一种适用于电源转换芯片的具有省电模式的CMOS振荡器电路,其特有的变频模式和间歇模式可以有效降低整个电源系统在轻载与空载时的功率损失,使得整个系统能随负载的变轻而线性降低开关频率,并在空载状态下进入间歇模式。基于SinoMOS1μm40V CMOS工艺,仿真和流片结果证明了该振荡器电路能够为电源转换系统芯片降低功耗提供所需要的功能,即根据负载情况自动调整PWM开关频率。     

Low-power digital communication with unterminated transmissionlines

Conventional telecommunication techniques are optimized to communicate over long distances (>1 mi), subject to high attenuation, high crosstalk, and other deteriorations in transmission. A trend in telecommunication system architectures is to disperse the previously centralized switching centers, thereby providing switching within a few hundred feet of the subscriber. This creates an opportunity for great improvements in cost and performance for short distance communication links. A technique for low-power digital communication over short transmission lines that exploits this possibility is described. The typical power is more than an order of magnitude lower than the power required with conventional circuits. Associated with this technique are a tenfold reduction in the chip area occupied by the transmission line drivers and the elimination of coupling transformers. The power and chip-area reductions result from terminating and maintaining an open circuit at the receiver. These advantages make this line-driving technique particularly suitable for single-chip VLSI systems     

Low-power design of decimation filters for a digital IF receiver

This paper presents low-power design techniques at the architectural level for design of decimation filters in a digital IF receiver for wide-area wireless data networks. A multimode decimation filter design implementing both Mobitex and Ardis networks is described. The power is reduced by a factor of 1422 and the area reduced by a factor of 7.85 compared to an optimized single-mode two-stage design. A new multistage decimation filter design tool is also presented, which compares alternative architectures on figures of merit which the low-power designer can map into technology-dependent area and power costs     

包含交流耦合CTIA与数字CDS的CMOS图像传感器设计

设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样（DCDS）结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声（FPN）。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。     

嵌入式数字存储示波器设计

提出了一种基于FPGA和STM32的嵌入式数字存储示波器设计,以STM32为控制核心,FPGA作为数据采集和处理模块,完成了对外部信号的采集和传输,实现了存储示波器数据处理和显示的功能.     

Low-power embedded SRAM with the current-mode write technique

In the traditional current-mode SRAMs, only the read operation is performed in the current mode. In this paper, we propose to use the current-mode technique in both the read and write operations. Due to the current mode operation, voltage swings at bit lines and data lines are kept very small during both read and write. Then, the ac power dissipation of bit lines and data lines, which is proportional to the voltage swing, can be significantly saved. A new current-mode 128×8 SRAM has been designed based on a 0.6 μm CMOS technology, and the new SRAM consumes only 30% of the power of an SRAM with current-mode read but voltage mode write operations. Besides a test chip for the new SRAM, it has also been embedded in an 8-bit 1.1-controller. Experimental results show good agreement with the simulation results and prove the feasibility of the new technique     

Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style     

Low-power programmable gain CMOS distributed LNA

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-/spl mu/m CMOS process. The LNA provides a flat gain, S/sub 21/, of 8 /spl plusmn/ 0.6dB from DC to 6.2 GHz, with an input impedance match, S/sub 11/, of -16 dB and an output impedance match, S/sub 22/, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.