对基于模代数的三值触发器的研究

本文用模代数讨论三值触发器。提出了基于模代数的三值 JK 触发器。与基于 Post代数的三值 JK 触发器相比,它的逻辑功能是均衡的,它能像二值 JK 触发器一样方便地构成另外二种常用的触发器:三值 D 型触发器与三值 T 型触发器。此外,由时序电路的设计实例,也证实了因它的功能较强而能导致较简单的激励函数与组合电路。     

基于U_h门的三值触发器和时序电路设计

本文根据基于模代数的各种三值触发器的次态方程,提出用U_k通用门实现各种三值触发器。在此基础上,利用U_k门阵列实现三值时序电路。     

适用于三值线性反馈移位寄存器的CMOS触发器

为了省免多值线性反馈移位寄存器中存在的常量乘运算电路，本文以三值逻辑为例，提出了具有Q-2Q双轨输出的三值CMOS触发器的设计，它可与传统的三值模和电路配合，即可实现三值线性反馈移位寄存器。这不仅简化了电路结构，并可提高电路的工作速度，PSPICE模拟证实了Q-2Q触发器设计具有正确的逻辑功能，此设计思想可推广至基数更高的多值线性反馈移位寄存器电路的设计。     

基于Uh门的三值触发器和时序电路设计

本文根据基于模代数的各种三值触发器的次态方程,提出用U_h通用门实现各种三值触发器。在此基础上,利用U_h门阵列实现三值时序电路。     

低功耗四边沿触发器设计

根据在保持电路原有性能的前提下可通过降低时钟频率来降低系统功耗的原理和双边沿触发器的设计思想,本文将多值信号信息量大的优点应用于时钟网络上设计了基于三值时钟的四边沿触发器,消除了三值时钟的冗余跳变,从而通过降低时钟频率的方式达到降低功耗的目的。本文设计的四边沿触发器电路结构简单,既可以用于二值时序电路中也可以用于多值时序电路中。模拟结果表明,本文设计的四边沿触发器具有正确的逻辑功能且能有效地降低系统功耗。     

基于门控时钟技术的低功耗三值D型触发器设计

本文在三值D型触发器的基础上提出了一种低功耗三值门控时钟D型触发器的设计.该设计通过抑制触发器的冗余触发来降低功耗,PSPICE模拟验证了该触发器具有正确的逻辑功能.与三值D触发器相比,该触发器在输入信号开关活动性较低的情况下具有更低的功耗.同时该电路结构可以推广到基值更高的低功耗多值触发器的设计中.     

多值模代数中的减法与除法运算及其应用

本文提出并讨论了模加与模乘运算的逆运算－模减与模除运算。它们的引入使模代数的取值域扩展到负数与分数，并以此建立相应的对称模代数与分数模代数系统。通过五值逻辑中函数表示的讨论，证明该二种新运算对建立一个功能完整的模代数系统是必要的。     

电流型CMOS脉冲D触发器设计

该文根据脉冲触发器的设计要求,结合阈算术代数系统,提出一种电流型CMOS脉冲D触发器的通用结构,用于二值及多值电流型CMOS脉冲触发器的设计,并可方便地应用于单边沿和双边沿触发。在此结构的基础上设计了电流型CMOS二值、三值以及四值脉冲D触发器。采用TSMC 180 nm CMOS工艺参数对所设计的电路进行HSPICE模拟后表明所设计的电路具有正确的逻辑功能和良好的瞬态特性,且较以往文献提出的电流型D触发器,优化了触发器的建立时间和保持时间,二值和四值触发器最差最小D-Q延时比相关文献的主从触发器降低了59.67%和54.99%,比相关文献的边沿触发器降低了4.62%以上,所用晶体管数也相对减少,具有更简单的结构以及更高的电路性能。     

基于多值模相关性的电流型CMOS电路设计

本文根据模相关性的性质，指出多值模代数系统中模无关。方程组有唯一解，矩阵可逆，函数的规范展开，模运算的完备性之间互为等价关系，并指导了四值单变量查函数的电流型ＣＭＯＳ电路设计，它比传统的成本法优越。     

基于U_h门的三值算术电路设计

本文利用基于模代数的三值通用逻辑门——U_k,设计了一位三值全加法器和全乘法器电路。     

DESIGN OF SYMMETRIC TERNARY CURRENT-MODE CMOS CIRCUITS

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.     

Impact of clock slope on true single phase clocked (TSPC) CMOScircuits

Clocked digital circuits are sensitive to changes of the input signals close to the clock transitions. Non ideal properties of the clock transition, such as slope, make timing requirements more complicated. Here we present methods, quantitative limits and clock buffer requirements by studying clock slope impact on TSPC circuits. The investigation is based on SPICE simulations of edge-triggered D flip-flops and latches, implemented in the TSPC technique. The simulation results were also verified by measurements on 2-μm CMOS prescalers     

DESIGN OF TERNARY FLIP-FLOPS AND SEQUENTIAL CIRCUITS BASED UPON U_h GATE

According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.     

RESEARCH INTO TERNARY EDGE-TRIGGERED JKL FLIP-FLOP

The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.     

时钟信号竞争型三值CMOS边沿触发器

本文利用时钟信号的竞争冒险现象,提出了CMOS时钟信号竞争型三值D型边沿触发器的逻辑设计.通过PSPICE程序模拟,证实了该设计具有正确的逻辑功能,而且与传统的三值D型维持阻塞触发器相比,它具有更简单的结构和更低的功耗.     

Theory of differential current switches and logic design of ternary ECL circuits at switch level

Starting from the viewpoint that the switch states and signal values in a digital circuit should be described separately by two different kinds of variable, the interaction between the switching element and signal in multi-valued ECL circuits is analysed and two types of connection operations, threshold switching operation and current switching operation, are proposed. The properties and circuit realizations of these new operations are discussed and the theory of differential current switches applicable to ECL circuits is established. Examples of basic ternary ECL circuits confirm that this theory can effectively guide the logic design of ternary ECL circuits at switch level. The circuits are verified by using the SPICE II program. They have the same logic level difference and transient characteristic as binary ECL circuits. Since the multi-valued ECL circuit uses only one set of power supply and can set several threshold values by using reference levels, it can be fabricated using conventional ECL techniques and is compatible with binary ECL circuits.     

A new family of semidynamic and dynamic flip-flops with embeddedlogic for high-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well     

Min-max timing analysis and an application to asynchronous circuits

Modern high-performance asynchronous circuits depend on timing constraints for correct operation, so timing analyzers are essential asynchronous design tools. In this paper we present a 13-valued abstract waveform algebra and a polynomial-time min-max timing simulation algorithm for use in efficient, approximate timing analysis of asynchronous circuits with bounded component delays. Unlike several previous approaches, our algorithm computes separate propagation delay bounds from each circuit input to each internal gate. This is useful for analyzing asynchronous circuits, where the relative transition times of the inputs may not be known a priori, unlike synchronous circuits. We also describe an efficient reconvergent fanout analysis technique that helps in increasing the accuracy of simulation. We have applied our algorithm to build an efficient timing analysis tool for extended burst-mode circuits (a class of timing-dependent asynchronous circuits) implemented in the 30 design style. Our tool analyzes gate-level 30 circuits assuming bounded component delays and determines safe timing constraints for correct operation. Although our results represent conservative approximations to the true timing requirements in the worst case, experiments indicate that our technique is efficient and fairly accurate in practice