硅纳米线纳米电子器件及其制备技术

硅纳米线由于特殊的光学及电学性能如量子限制效应及库仑阻塞效应等,在纳米电子器件的应用方面具有潜在的发展前景。介绍了采用电子束蚀刻技术(EB)、反应性离子蚀刻技术(RIE)、金属有机物化学气相沉积(MOCVD)等制备技术及场效应晶体管、单电子探测器及存储器、双方向电子泵及双重门电路等硅纳米线纳米电子器件的最新进展情况,并对其发展前景作了展望。     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

金属纳米晶快闪存储器研究进展

金属纳米晶具有态密度高、费米能级选择范围广以及无多维载流子限制效应等优越性,预示着金属纳米晶快闪存储器在下一代闪存器件中具有很好的应用前景。从金属纳米晶存储器的工作原理、纳米晶的制备方法、以及新型介质材料和电荷俘获层结构等方面,对金属纳米晶存储器近年来的研究进展进行了总结。     

纳米结构制备技术

随着纳米加工技术的发展,纳米结构器件必将成为将来的集成电路的基础.本文介绍了几种用电子束光刻、反应离子刻蚀方法制备硅量子线、量子点和用电子束光刻、电子束蒸发以及剥离技术制备纳米金属栅的工艺方法;用这种工艺方法在P型SIMOX硅片上成功制造的一种单电子晶体管,在其电流电压-特性上观测到明显的库仑阻塞效应和单电子隧穿效应.     

利用同步晶化法制备的镍纳米晶的电荷存储特性

快速退火纳米晶化法是目前常用的金属纳米晶制备方法,但其后续600~900℃高温退火会降低器件的电学特性和可靠性。本文提出了热预算低的金属纳米晶制备的新方法—沉积过程中的同步金属薄膜原位纳米晶化法,可以省掉后续单独的退火处理工艺,使金属薄膜同步产生纳米晶化,降低工艺热功耗及简化工艺,从而有效地改善上述薄膜沉积后退火纳米晶化法的不足。在不同衬底温度（250~325 ?C）下,利用同步纳米晶化法制备镍纳米晶存储器。随着生长温度的增加,其存储窗口先增加到最大值再降低。衬底温度为300 ?C时,其存储窗口（2.78 V）最大。与快速热退火法镍纳米晶存储器相比较,同步纳米晶化法制备镍纳米晶存储器具有更强的电荷存储能力。另外,研究了不同操作电压和脉冲时间下器件的平带电压偏移量,当操作电压增加到±10 V时出现了较大的平带电压偏移量,这表明器件发生了大量的载流子（电子和空穴）注入现象。最后,模拟了金属纳米晶存储器的载流子（电子和空穴）注入和释放过程。     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

纳米存储器的多值逻辑设计研究

为探索解决纳米技术发展的极限问题,讨论纳米技术发展的极限和二值逻辑设计的存储器结构,为应对纳米器件在到硅技术7 nm极限的突破,提出基于二端单电子晶体管的库仑台阶效应的多值逻辑设计的纳米存储器模型,分析9值逻辑逻辑设计的单位纳米存储器的逻辑信号与输出电压之间的关系,发现这样构建的存储矩阵大小几乎成几何级减小,提高了信息密度.     

基于重核衰变原理的单电子存储器寿命模型

单电子存储器是依据库仑阻塞原理操纵单个电子进行信息存储的一种量子器件。它具有低功耗、高速度、极小尺寸的优点,是现有存储器极有希望的替代品。信息的记忆性能是衡量存储器的一个重要参数,因而对单电子存储器的记忆性能研究有重要的意义。存储器的结构以及温度、电磁辐射等环境因素都对单电子存储器记忆时间产生影响,因而有必要寻求一种模型来综合各种因素对储存器存储寿命的影响。借鉴Gamow、Gurney和Condon处理某些重核α粒子自然衰变的方法对单电子存储器的记忆能力进行研究,考虑到了环境参数和结构参数对记忆性能的影响,给出了一种新的单电子存储器记忆时间模型,并对该模型进行详细的理论分析。     

浅谈半导体量子点与纳米电子学

浅谈半导体量子点与纳米电子学王家俭（山东大学物理系济南２５０１００）关键词量子点，库仑阻塞现象，单电子晶体管，纳米电子学目前，以集成电路为基础的微电子技术，已在国民经济和现代战争中起到不可估量的作用。随着电路尺寸不断缩小、集成度的提高，已进入甚大规模...     

Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance

The write/erase characteristics of Germanium nanocrystal memory device are modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects. A trap model is proposed to describe the retention characteristic of the nanocrystal memory. The impact of nanocrystal size, tunnel-oxide thickness, and high-k tunnel material is studied, and the suitability of the nanocrystal memory devices for nonvolatile memory and DRAM applications is discussed. Issues related to the scaling limit of the nanocrystal memory device are investigated.     

Nonvolatile Si quantum memory with self-aligned doubly-stacked dots

We propose a novel Si dot memory whose floating gate consists of self-aligned doubly stacked Si dots. A lower Si dot exists immediately below an upper dot and lies between thin tunnel oxides. It is experimentally shown that charge retention is improved compared to the usual single-layer Si dot memory. A theoretical model considering quantum confinement and Coulomb blockade in the lower Si dot explains the experimental results consistently, and shows that charge retention is improved exponentially by lower dot size scaling. It is shown that the retention improvement by lower dot scaling is possible, keeping the same write/erase speed as single dot memory, when the tunnel oxide thickness is adjusted simultaneously.     

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.     

Simulation of a cobalt silicide/Si hetero-nanocrystal memory

A nanocrystal memory using CoSi₂/Si hetero-nanocrystals as floating gate was proposed. Numerical investigations on the writing, erasing and retention were performed. The hetero-structure provides an extra quantum well for the charge to achieve much longer retention time while maintains a writing/erasing speed similar to that of Si nanocrystal memory.     

Local tunneling spectroscopy of silicon nanostructures

The recharging of many-hole and few-electron quantum dots under the conditions of the ballistic transport of single charge carriers inside self-assembled quantum well structures on a Si (100) surface are studied using local tunneling spectroscopy at high temperatures (up to room temperature). On the basis of measurements of the tunneling current-voltage characteristics observed during the transit of single charge carriers through charged quantum dots, the modes of the Coulomb blockade, Coulomb conductivity oscillations, and electronic shell formation are identified. The tunneling current-voltage characteristics also show the effect of quantum confinement and electron-electron interaction on the characteristics of single-carrier transport through silicon quantum wires containing weakly and strongly coupled quantum dots.     

Impact of high-κ dielectric and metal nanoparticles in simultaneous enhancement of programming speed and retention time of nano-flash memory

A methodology to simulate memory structures with metal nanocrystal islands embedded as floating gate in a high-κ dielectric material for simultaneous enhancement of programming speed and retention time is presented. The computational concept is based on a model for charge transport in nano-scaled structures presented earlier, where quantum mechanical tunneling is defined through the wave impedance that is analogous to the transmission line theory. The effects of substrate-tunnel dielectric conduction band offset and metal work function on the tunneling current that determines the programming speed and retention time is demonstrated. Simulation results confirm that a high-κ dielectric material can increase programming current due to its lower conduction band offset with the substrate and also can be effectively integrated with suitable embedded metal nanocrystals having high work function for efficient data retention. A nano-memory cell designed with silver (Ag) nanocrystals embedded in Al₂O₃ has been compared with similar structure consisting of Si nanocrystals in SiO₂ to validate the concept.     

Metal nanocrystal memory with high-/spl kappa/ tunneling barrier for improved data retention

A nonvolatile memory (NVM) with metal nanocrystal (NC) embedded in high-/spl kappa/ dielectrics is proposed. With the larger work function of the metal NC compared to that of silicon NC, the metal NC memory exhibits the better data retention characteristic. The theoretical analysis showing the effect of the electron barrier height on tunneling current density is also presented to support the importance of work function engineering of the NC in NVM structure. The other electrical characteristics such as the programming transient and data endurance are also studied and described in this paper.