基于边界扫描技术和TCL语言的簇测试设计

在边界扫描测试技术中,由BS器件和非BS器件主成的逻辑簇测试是研究的难点问题,文章介绍了高效、简明、移植性好的TCL语言.在深入研究边界扫描簇测试原理的基础上,以实现逻辑簇测试为目的,采用了TCL嵌入C++的方法实现测试用例的脚本化,完成了基于TCL语言的Cluster测试脚本设计;通过对数字电路实验板的测试结果分析,得到了使用TCL脚本语言与C++联合编程能够实现簇测试,并且可以提高边界扫描测试软件工作效率的结论,具有较好的应用前景。     

FPGA的虚拟JTAG技术对并口FLASH快速编程

集成数字电路板上经常有FLASH器件需要编程,在工厂批量生产中往往要占据较多时间.特别是对于挂载在可编程器件(FPGA)的并行接口的FLASH,使用边界扫描的方法靠移位数据来仿真FLASH读写时序,从而完成FLASH器件编程的方法相当低效费时.应用了虚拟JTAG技术后,就不需要进行整个边界引脚的移位处理,可以一次性从JTAG链上加载较大的数据块,再配合并口FLASH的接口逻辑进行编程,有效地提高了效率.     

一种新型JTAG数据的快速加载方法

为解决传统边界扫描测试诊断软件在加载测试数据时出现不稳定而影响测试结果的问题,通过对边界扫描技术的研究和对传统边界扫描测试方法的分析,在实验中发现测试数据经过外部动态缓存和外部时钟的统一触发后不仅可以消除数据的不稳定性还可以得到可调的测试频率,在此基础上,利用微处理器和可编程逻辑器件的协同控制,设计了一种基于USB协议的JTAG端口测试数据快速加载方法;系统仿真和实验结果表明,加载数据稳定可靠,取得了比一般加载方法更好的效果.     

带有非边界扫描器件的混装电路的扫描链优化配置

在混装电路中,由不同的非边界扫描器件所组成的簇所需要的测试向量的数目可能是不同的,根据不同的簇所需要的测试向量的不同,可以将整个测试过程分为不同的测试阶段,每个测试阶段过后都会有一个或者多个扫描芯片处于bypass状态,而此时其长度只有1,也就是说每一个扫描链的长度是随着测试矢量的移出而变化的,整个扫描链的配置过程中,需要考虑这样两个问题：如何将扫描芯片分配给各条扫描链以及如何排列各条扫描链中扫描芯片的顺序,提出了一种如何配置单链的方法,即优化配置扫描芯片在扫描链中的顺序,这种方法同样可以被应用到多链.     

类蜂巢结构快速样机平台的可测试性设计

类蜂巢结构快速样机平台(HLRESP)是一个基于现场可编程门阵列(FPGA)的通用样机平台，采用类似蜂窝状的系统结构。根据该样机平台特点，采用边界扫描技术进行板级和系统级的可测试性设计，扫描链路可以灵活配置，不仅能实现边界扫描测试，还能实现对可编程器件的在线编程，方便了样机平台的测试和调试工作，缩短了系统开发周期。     

用户定制边界扫描结构的设计与自动实现

边界扫描是一种标准化的可测性设计体系结构,已被广泛应用于板级测试、系统片上调试以及IC编程;Longtium R2+微处理器的边界扫描设计采用EDA工具BSD Compiler自动完成,缩短了设计和验证周期;主要介绍了BSD Compiler的设计流程及配置要点,并结合Longtium R2+边界扫描逻辑的具体实现方案,提出了一种利用边界扫描逻辑实现对系统内部逻辑观察与控制的机制。     

基于FPGA的电路板自动测试技术研究

军用电子装备中含FPGA器件的电路板的测试诊断一般采用边界扫描技术、Ⅵ曲线测试技术以及边界扫描和外部输入矢量相结合的方法;边界扫描技术无法进行外围器件的测试;Ⅵ曲线测试技术由于不能测试器件的逻辑功能及内部节点,故障覆盖率相对不高;边界扫描和外部输入矢量相结合的方法无法判断FPGA器件工作是否正常,因而不能完成整板功能的测试;综合应用ATE技术、VITAL标准和LASAR仿真技术,提出一种含FPGA器件电路板的自动测试思路,解决含FPGA器件电路板的自动测试问题.     

基于SQLite的边界扫描互连测试矢量生成设计

互连测试是边界扫描技术的主要内容之一,在分析IEEE1149.1的基础上,给出一种基于嵌入式开源数据库SQLite的边界扫描测试系统中互连测试矢量生成的设计;利用SQLite数据库中存储的被测电路的扫描链路信息和器件等信息,得到扫描粗链并进一步形成扫描细链;利用可测网络信息结合测试算法产生测试矢量;最终将测试矢量在扫描细链上对扫描单元赋值即得到扫描链的互连测试矢量集;测试结果表明,该设计可快速生成测试矢量而缩短测试时间,具有较好的应用前景.     

基于虚拟扫描链的混合信号电路测试方法研究

针对目前存在的混合信号电路测试效率不高的现象,在混合信号测试总线(IEEE1149.4标准)基础上引入虚拟扫描链的思想,并构建了一种混合信号虚拟边界扫描测试结构,在详细阐述该结构的工作原理基础上,在Quartus II软件中对混合信号虚拟边界扫描测试结构的功能性测试流程进行了仿真;通过仿真验证表明该结构完全兼容IEEE1149.4标准中的指令,对促进边界扫描技术的发展具有积极的意义。     

混合技术电路板簇测试的多边界扫描链优化配置

由边界扫描器件和非边界扫描器件组装的混合技术电路板将在今后相当长时间内广泛存在,析台由非边界扫描器件组成的簇的测试是边界扫描测试领域重要而富有实际价值的问题。为减少其测试时间,基于贪婪策略和单扫描链最优排序技术,提出了一种多边界扫描链优化配置技术,经实例验证表明,该技术可以有效地减少混合技术电路板族测试时间,提高测试效率。     

蚁群优化在组合电路测试生成中的应用

如何高效地解决数字电路测试生成问题是VLSI领域中的核心。通过对蚁群算法在不同类型的组合优化和搜索问题上的应用研究,基于组合电路测试的路径敏化方法,借助SAT确定性算法工具,提出了一个新的蚁群算法模型来解决组合电路测试生成问题,并通过实验验证其可行性。     

Wavelet based fault detection in analog VLSI circuits using neural networks

This paper deals with a new method of testing analog VLSI circuits, using wavelet transform for analog circuit response analysis and artificial neural networks (ANN) for fault detection. Pseudo-random patterns generated by Linear Feedback Shift Register (LFSR) are used as input test patterns. The wavelet coefficients obtained for the fault-free and faulty cases of the circuits under test (CUT) are used to train the neural network. Two different architectures, back propagation and probabilistic neural networks are trained with the test data. To minimize the neural network architecture, normalization and principal component analysis are done on the input data before it is applied to the neural network. The proposed method is validated with two IEEE benchmark circuits, namely, the operational amplifier and state variable filter.     

基于典型集成电路的自动测试演示验证研究

当前国产超大规模集成电路测试设备由于技术指标、工作可靠性、制造成本等诸多因素,在国内尚未得到大规模的市场应用;从集成电路的测试需求出发,给出了自研超大规模集成电路测试系统的总体架构组成,重点开展了基于典型集成电路的自动测试演示验证方法研究,并以国产某型超大规模静态存储器芯片作为演示验证的对象,利用自研测试系统完成了基于静态存储器芯片的自动测试演示验证试验;试验结果表明基于典型集成电路的自动测试演示验证方法和过程合理可行,能够为国产新研超大规模集成电路测试系统推广前的自动测试演示验证提供参考,同时可结合不同类型集成电路的测试需求深入应用到各类集成电路的测试过程。     

Testing and built-in self-test – A survey

As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This built-in self-test (BIST) approach not only offers economic benefits but also interesting technical opportunities with respect to hierarchical testing and the reuse of test logic during the application of the circuit.Starting with an overview of test problems, test applications and terminology this survey reviews common test methods and analyzes the basic test procedure. The concept of BIST is introduced and discussed, BIST strategies for random logic as well as for structured logic are shown.     

Application of fuzzy logic in resistive fault modeling and simulation

Real defects (e.g., resistive stuck at or bridging faults) in very large-scale integration (VLSI) circuits cause intermediate voltages which cannot be modeled as ideal shorts. In this paper, we first show that the traditional zero-resistance model is not sufficient for fault simulation. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate level. Our method uses Takagi-Sugeno (TS) fuzzy system to accurately model digital VLSI circuits and produces much more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test-pattern statistics for the ISCAS85 benchmarks.     

Using a periodic square wave test signal to detect crosstalk faults

Built-in self test (BIST) scheme simplifies the detection of crosstalk faults in deep-submicron VLSI circuits in the boundary scan environment. The scheme tests for crosstalk faults with a periodic square wave test signal under applied random patterns generated by a linear feedback shift register (LFSR), which is transconfigured from the embedded circuit's boundary scan cells. The scheme simplifies test generation and test application while obviating the fault occurrence timing issue. Experimental results show that coverage for the induced-glitch type of crosstalk fault for large benchmark circuits can easily exceed 90%.     

DNA and quantum based algorithms for VLSI circuits testing

Testing of VLSI circuits is still a NP hard problem. Existing conventional methods are unable to achieve the required breakthrough in terms of complexity, time and cost. This paper deals with testing the VLSI circuits using natural computing methods. Two prototypical algorithms named as DATPG and QATPG are developed utilizing the properties of DNA computing and Quantum computing, respectively. The effectiveness of these algorithms in terms of result quality, CPU requirements, fault detection and number of iterations is experimentally compared with some of existing classical approaches like exhaustive search and Genetic algorithms, etc. The algorithms developed are so efficient that they require only N (where N is the total number of vectors) iterations to find the desired test vector whereas in classical computing, it takes N/2 iterations. The extendibility of new approach enables users to easily find out the test vector from VLSI circuits and can be adept for testing the VLSI chips.     

一种保留进位阵列乘法器的分析

复杂的VLSI电路的分析,对设计验证、故障诊断与测试都至关重要.对于一个用某种连结性语言描述的几千个门以上的电路,除了用CAD工具去处理之外,人们对它无法理解,没有直观的印象.电路图很难画,画出来也很难读懂.因此,与自顶向下的设计相反,研究自下而上的分析方法很有必要.本文介绍一种电路的结构分析方法.基于此方法,我们分析出国际通用的ISCAS十个电路实例中的C6288是一种保留进位阵列乘法器.因而对C6288的功能、结构都搞得一清二楚.     

The Methodology of Testability Prediction for Sequential Circuits

Increasingly,test generation algorithms are being developed with the continuous creations of incredibly sophisticated computing systems.Of all the developments of testable as well as reliable designs for computing systems,the test generation for sequential circuits is usually viewed as one of the hard nuts to be solved for its complexity and time-consuming issue.Although dozens of algorithms have been proposed to cope with this issue,it still remains much to be desired in solving such problems as to determin 1) which of the existing test generation algorithms could be the most efficient for some particular circuits(by efficiency,we mean the Fault Coverage the algorithm offers,CPU time when executing,the number of test patterns to be applied,ectc.)since different algorithms would be preferable for different circuits;2)which parameters(such as the number of gates,flip-flops and loops,etc., in the circuit)will have the most or least influences on test generation so that the designers of circuits can have a global understanding during the stage of designing for testability.Testability forecastin methodology for the sequential circuits using regression models is presented which a user usually needs for analyzing his own circuits and selecting the most suitable test generation algorithm from all possible algorithms available.Some examples and experiment results are also provided in order to show how helpful and practical the method is.