A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz

A charge-domain quadrature sampling circuit realization in 0.35 /spl mu/m CMOS is presented. The circuit downconverts a real-valued IF input signal with a nominal frequency of 50 MHz into baseband quadrature components by decimation. Based on multiple integrative sampling of charge, the circuit integrates a 192-tap complex bandpass finite-impulse response filtering function into the sampling operation providing 18 dB of built-in anti-aliasing suppression for the nearest unwanted frequencies aliasing to dc and over 36 dB of image band rejection on the 923-kHz 3-dB bandwidth of the circuit. The measured third-order input intercept point is + 25 dBV at 50 MHz, while the spurious-free dynamic range is more than 66 dB up to 100-MHz IF input frequency. The power consumption excluding output buffers is 30 mW from a 3.3-V supply.     

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g_m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g_m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm². Experimental results are presented to validate the proposed circuit.     

A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR

This paper presents a second-order ΔΣ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-μm, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the art performance in CMOS technology optimized for digital circuits     

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.     

一种SFDR为83.5dB的14位100兆流水线模数转换器

This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC）. The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.     

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current–voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-$muhbox{m}$ CMOS process, the transconductor occupies 220 $,times,$160 $muhbox{m}^{2}$ active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.      

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over80-dB SFDR

A 12-b analog-to-digital converter (ADC) is optimized for spurious-free dynamic range (SFDR) performance at low supply voltage and suitable for use in modern wireless base stations. The 6-7-b two-stage pipeline ADC uses a bootstrap circuit to linearize the sampling switch of an on-chip sample-and-hold (S/H) and achieves over 80-dB SFDR for signal frequencies up to 75 MHz at 50 MSample/s (MSPS) without trimming, calibration, or dithering. INL is 1.3 LSB, differential nonlinearity (DNL) is 0.8 LSB. The 6-b and 7-b flash sub-ADCs are implemented efficiently using offset averaging and analog folding. In 0.6-μm CMOS, the 16-mm² ADC dissipates 850 mW     

A CMOS line driver with 80-dB linearity for ISDN applications

A high-performance CMOS line driver for ISDN U-interface transceiver applications has been designed and fabricated. Careful study of requirements and trade-offs affecting linearity, power efficiency, and quiescent current presented in this work has resulted in a circuit structure featuring a highly linear input/output characteristic and well-controlled quiescent current. The prototype line driver is capable of delivering a 5-V_pp signal of up tp 80 kHz to a 60-Ω load while exhibiting linearity on the order of 77 ± 5 dB and operating from a single 5-V power supply. Linearity better than 70 dB is maintained for load resistances as low as 20 Ω     

A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption

This work describes a method for analysis of voltage-to-current converters (V-I converters or transconductors) and a novel V- I converter circuit with significantly improved linearity. The new circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third- and fifth-order harmonic distortion components in the transconductor characteristics. An evaluation of the optimal circuit dimensioning is shown. Simple and robust design rules are derived for the chosen operation conditions. The transistor implementation is presented and a prototype V- I converter is realized in a digital 0.18-/spl mu/m CMOS technology. The measured spurious-free dynamic range is 75 dB in a frequency band of 10 MHz. The circuit occupies less than 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.     

A CMOS switched transconductor mixer

A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-/spl mu/m CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.     

A 100-dB SFDR 80-MSPS 14-Bit 0.35-$ muhbox m$BiCMOS Pipeline ADC

This paper describes a 14-bit 80-MSPS ADC with 100-dB SFDR at 70-MHz input frequency in a 0.35-$muhbox m$single-well BiCMOS technology drawing 1.2 W from a dual 3.3 V/5.0 V supply. Key barriers to high dynamic range in pipeline ADCs at high clock rates and some methods to overcome these barriers will be presented. These methods include a sampling front-end without the use of a designated Sample and Hold (S/H). A BiCMOS switching input buffer is used along with the strategic use of BiCMOS design techniques. Also, calibration is combined with capacitor shuffling to maximize linearity with minimal noise impact.     

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquistinput

This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-μm double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm² ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V     

A compact tunable CMOS transconductor with high linearity

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-/spl mu/m CMOS technology show a total harmonic distortion of -54 dB at 100 kHz for an 80-/spl mu/A peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm/sup 2/ of silicon (Si) area and features 0.96 mW of static power consumption.     

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.     

一种具有84.8dB SFDR和72dB SNDR的14位80MS/s CMOS模数转换器

本文描述了一种基于0.35μm CMOS工艺的14位采样率80MS/s的流水线型模数转换器的设计. 所提出的电荷分享校正技术消除了与信号相关的电荷注入效应, 加上片内的低抖动时钟电路, 保证了模数转换器的高动态性能. 一种信号电容开关技术和高对称版图减小了电容失配, 确保了模数转换器的总线性度. 测试结果表明, 该模数转换器在36.7MHz输入频率下, 实现了11.6位的有效位, 84.8dB的无杂散动态范围(SFDR), 72dB的信号噪声失真比(SNDR), 在无校准情况下获得了＋0.63/－0.6 LSB的微分非线性和＋1.3/－0.9 LSB的积分非线性. 输入频率200MHz时,仍然可以保持75dB的SFDR和59dB的SNDR.     

An undersampling 14-bit cyclic ADC with over 100-dB SFDR

A high linearity, undersampling 14-bit 357 kSps cyclic analog-to-digital convert (ADC) is designed for a radio frequency identification transceiver system. The passive capacitor error-average (PCEA) technique is adopted for high accuracy. An improved PCEA sampling network, capable of eliminating the crosstalk path of two pipelined stages, is employed. Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area. An additional digital calibration block is added to compensate for the error due to defective layout design. The presented ADC is fabricated in a 180 nm CMOS process, occupying 0.65 × 1.6 mm~2.The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range (SFDR),and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.     

SFDR高于100dB的14位欠采样循环模数转换器

本文为射频标签(RFID)收发机系统设计了一个高线性,14位357 k采样率的欠采样循环模数转换器。为提高模数转换器的精度,设计中采用了有源电容误差平均(PCEA)技术。并且提出了一种改进的PCEA采样网络,可以消除两个流水级之间的串扰影响。为降低模数转换器的功耗和减小面积,设计采用了运放共享技术,并且去除了采样保持放大级。为补偿不完善的版图设计引入的误差,增加了一个附加的数字校准模块。该模数转换器由180 nm CMOS工艺流水完成,面积为0.65 mm  1.6 mm。在确保SFDR不低于90 dB的条件下,该欠采样模数转换器的输入信号频率高达15.5 MHz;在2.431 MHz输入下,峰值SFDR高达106.4 dB.     

A 12-bit self-calibrating SAR ADC achieving a Nyquist 90.4-dB SFDR

This paper describes a 10 or 12 bit programmable successive approximation register ADC for bridge stress monitoring systems requiring high-resolution, high linearity, low power and small size. Its sampling rate is scalable, from 0 to 200 kS/s. The proposed ADC employs a novel time-domain comparator with offset cancellation. Prototyped in a 0.18-μm, 6MIP CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 68.74 dB (11.13), an SFDR of 90.36 dB, while dissipating 579.6 μW from a 1.8-V supply. The on-chip calibration improves the DNL from +0.2/?0.74 LSB to +0.23/?0.25 LSB and INL from +1.27/?0.97 LSB to +0.41/?0.4 LSB.     

10 MHz CMOS OTA-C voltage-controlled quadrature oscillator

A quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C) is presented. A monolithic integrated CMOS test circuit is introduced to verify theoretical results. The attainable frequency range of oscillation of the chip test circuit is 3-10.34 MHz. The total harmonic distortion (THD) is 0.20-1.87% for corresponding peak-to-peak amplitude voltages between 100 mV and 1 V. This amplitude can be controlled either by using a diode connection of two MOS transistors or a proposed nonlinear resistor.<>     

A versatile CMOS linear transconductor/square-law function

A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.