网络处理器体系结构分析

该文旨在分析网络处理器能够同时满足高性能和灵活性要求的体系结构。而传统的网络设备单纯采用专用芯片或者基于RISC的通用处理器(GPPs),很难兼顾这两者要求。该文根据网络处理器的处理空间,将其映射为5个逻辑模块,这些模块由网络处理器中各个功能部件实现。然后分析了网络处理器的SMP和Pipeline两种并行结构,并进一步分析了隐藏延迟等实现加速的技术。最后分析了网络应用发展变化对网络处理器体系结构设计的挑战,并提出了解决办法。     

网络处理器的分析与研究

目前,网络在提高链路速率的同时出现了大量的新协议及新服务,而传统的网络设备一般采用专用硬件芯片或者基于纯粹的软件方案,很难兼顾性能与灵活性两方面的要求.为此,一种并行可编程的网络处理器被引入到路由器(交换机)的处理层面.它基于ASIP技术对网络程序处理进行了优化,同时还兼有硬件和软件两种方案的特点.网络处理器的出现将经典的\"存储-转发\"结构变为\"存储-处理-转发\",这为复杂的QoS控制和负载处理提供了可能.从网络处理器本身及其应用两个角度出发,介绍了相关的研究工作,分析了系统特点和面临的挑战,并展望其未来的发展方向.     

新一代网络处理器体系结构研究

在对现有的网络处理器体系结构进行研究的基础上,提出了新一代网络处理器的顶层体系结构,该体系结构具有流式处理、基于端口(Port)的指令以及任务切换零延时等特点。     

网络处理器体系结构分析与研究

网络处理器兼顾了ASIC芯片的高性能和RISC的可编程及灵活性,能同时提供较好的处理速度和丰富的业务支持,因而广泛应用于各种网络通信设备中。文章主要对当前主流的网络处理器体系结构的系统架构和关键技术进行了综合的分析和评价,同时对网络处理器体系结构发展方向做出了展望。     

网络处理器的体系结构技术研究

介绍了网络处理器的现状及发展趋势，在分析当前网络处理器发展所面临的主要问题的基础上提出了一种新型网络处理器结构。     

网络处理器体系结构的比较与分析

网络处理器作为路由器设计的关键部分,不仅具有ASIC的功能,同时有着通用CPU的编程能力,在速度与可编程方面均有着优良的性能。该文主要阐述IBM NP4GS3与Intel IXP 1200两款网络处理器的体系结构,并对网络处理器的总线设计、微引擎机制、存储器设计等关键部分加以比较分析,为设计网络处理器提供参考。     

基于SystemC的网络处理器体系结构建模方法

随着各种新的网络业务不断出现,网络处理器得到了日益广泛的应用。文章采用基于SystemC的系统设计方法,构建一个用于网络处理器体系结构建模的平台。这个平台由一个可扩展的异构资源库和一个体系结构构造器组成。设计者只需提交配置信息表,体系结构构造器就能自动生成模型实例,得到的模型可以方便地进行细化和性能评价。这种方法能够便捷地完成各种网络处理器的体系结构建模,便于网络处理器的优化设计。     

粗粒度数据流网络处理器体系结构及原型系统设计

网络处理器是一种支持高速报文处理和转发的可编程通信集成电路.作为路由器中的重要组件,网络处理器设计不但强调高性能,还要求足够的灵活性以支持未来的网络协议.针对控制流网络处理器固定拓扑结构及指令级并行性开发方面的不足,采用粗粒度数据流设计思想,提出了一种粗粒度数据流网络处理器体系结构及原型--DynaNP.DynaNP不但可利用处理引擎内控制流执行方式获得高可编程性,还利用处理引擎间数据流执行方式有效开发报文处理中的任务级并行性.此外,DynaNP提供了处理路径动态配置机制,可有效提高系统流量.DynaNP的原型系统基于SoPC技术设计实现.多个PE和功能模块通过片上高速通信网络连接,其中,核心处理引擎采用嵌入式RISC处理器核LEON3实现,并采用指令集扩展技术优化网络协议处理.该原型系统可有效验证粗粒度数据流网络处理器的功能和关键技术.     

网络处理器中协处理器设计方法研究及实现

随着深亚微米工艺的迅速发展,现代网络处理器芯片广泛采用MPSoC体系结构实现。针对网络处理器中协处理器的特点,本文研究了其设计方法,提出了三种多个处理单元间的协处理器共享机制,而后在基于NiosⅡ软核的网络处理器中实现了多种协处理器结构,以支持不同的设计需求。     

网络处理器中处理单元的设计与实现

随着网络带宽的飞速增长和各种新的网络应用不断涌现,原有的基于通用处理器和ASIC的互联网架构已经不能满足新的需求。兼具强大处理能力和灵活可编程配置能力的网络处理器逐渐得到广泛的应用。高性能的网络处理器通常采用多个并发的处理单元进行数据平面的快速处理,这些处理单元在网络处理器中居于核心的地位。该文讨论了网络处理器中处理单元设计需要考虑的因素,设计了一种较为灵活有效的处理单元架构,并进行了FPGA原型验证,证实了该结构的可行性。     

Connected component labelling on the BLITZEN massively parallel processor

This paper presents the implementation of two connected component labelling algorithms on the BLITZEN massively parallel processor that was developed recently for NASA. The topology of BLITZEN is a two-dimensional mesh that can be dynamically configured to also support diagonal data transfers. It is shown that an algorithm based on Levialdi's connected component shrinking process performs much better than a straightforward algorithm for connected component labelling.     

The architecture of a multi-vector processor system, VPP

The VPP system is a multi-vector processor system which mainly aims at effective satellite image processing. It consists of up to 64 element processors (PUs), an S-D loop network, and an image memory. The PUs can execute flexible vector processing by a new vector access method, ‘Index-set’. The S-D loop network achieves high-speed and contention-free data transfer among the PUs. With these components, a new method for parallel processing, ‘Processor Pipeline’, can be realized on the VPP system.     

On the impact of network latency on distributed systems design

Research in distributed database systems to date has assumed a “variable cost” model of network response time. However, network response time has two components: transmission time (variable with message size) and latency (fixed). This research improves on existing models by incorporating a “fixed plus variable cost” model of the network response time. In this research, we: (1) develop a distributed database design approach that incorporates a “fixed plus variable cost”, network response time function; (2) run a set of experiments to create designs using this model, and (3) evaluate the impact the new model had on the design in various types of networks. This revised version was published online in July 2006 with corrections to the Cover Date.     

Parallel stereocorrelation on a reconfigurable multi-ring network

A reconfigurable network termed as the reconfigurable multi-ring network (RMRN) is described. The RMRN is shown to be a truly scalable network in that each node in the network has a fixed degree of connectivity and the reconfiguration mechanism ensures a network diameter of O(log₂ N) for anN-processor network. Algorithms for the two-dimensional mesh and the SIMD or SPMD n-cube are shown to map very elegantly onto the RMRN. Basic message passing and reconfiguration primitives for the SIMD/SPMD RMRN are designed for use as building blocks for more complex parallel algorithms. The RMRN is shown to be a viable architecture for image processing and computer vision problems using the parallel computation of the stereocorrelation imaging operation as an example. Stereocorrelation is one of the most computationally intensive imaging tasks. It is used as a visualization tool in many applications, including remote sensing, geographic information systems and robot vision.An earlier version of this paper was presented at the 1995 International Conference on Parallel and Distributed Processing Techniques and Applications.     

Parallel computer vision on Polymorphic Torus architecture

Polymorphic Torus is a novel interconnection network for SIMD massively parallel computers, able to support effectively both local and global communication. Thanks to this characteristic, Polymorphic Torus is highly suitable for computer vision applications, since vision involves local communication at the low-level stage and global communication at the intermediate- and high-level stages. In this paper we evaluate the performance of Polymorphic Torus in the computer vision domain. We consider a set of basic vision tasks, namely,convolution, histogramming, connected component labeling, Hough transform, extreme point identification, diameter computation, andvisibility, and show how they can take advantage of the Polymorphic Torus communication capabilities. For each basic vision task we propose a Polymorphic Torus parallel algorithm, give its computational complexity, and compare such a complexity with the complexity of the same task inmesh, tree, pyramid, and hypercube interconnection networks. In spite of the fact that Polymorphic Torus has the same wiring complexity as mesh, the comparison shows that in all of the vision tasks under examination it achieves complexity lower than or at most equal to hypercube, which is the most powerful among the interconnection networks considered.     

基于流处理器的图像灰度变换并行处理研究

提出了一种基于流处理器的图像灰度变换并行处理系统.该系统采用Strom-1 系列SP16HP-G220流数字信号处理器构建硬件平台,根据流处理器体系结构特点建立了适应图像灰度变换并行处理的流程序模型,并对图像灰度变换进行算法并行性分析与算法流化.对利用流化过的算法与传统灰度变换算法进行了对比实验.实验结果表明,灰度变换...     

A continuation-based noninterruptible multithreading processor architecture

Current trend of research on multithreading processors is toward the chip multithreading (CMT), which exploits thread level parallelism (TLP) and improves performance of softwares built on traditional threading components, e.g., Pthread. There exist commercially available processors that support simultaneous multithreading (SMT) on multicore processors. But they are basically based on the conventional sequential execution model, and execute multiple threads in parallel under the control of OS that handles interruptions. Moreover, there exist few languages or programming techniques to utilize the multicore processors effectively. We are taking another approach to develop a multithreading processor, which is dedicated to TLP. Our processor, named Fuce, is based on the continuation-based multithreading. A thread is defined as a block of sequentially ordered instructions which are executed without interruption. Every thread execution is triggered only by the event called continuation. This paper first introduces the continuation-based multithread execution model and its processor architecture then gives multithreaded programming techniques and the continuation-based multithreading language system CML. Last, the performance of the Fuce processor is evaluated by means of the clock-level software simulation.     

主动网络体系结构的探讨与实现

描述一种新型的可编程网络体系结构——主动网络.它可以根据网络应用和服务的要求,对网络进行编程,因而大大加快了新网络应用和服务的实现.并介绍主动网络的概念和体系结构,以及基于主动网络的应用及实现方法：可编程交换机方法（分散式）和封装（Capsule）（或集中式）方法.