具有加长LDD结构的高压CMOS器件

基于中国科学院微电子研究所的0.8μm标准N阱CMOS工艺以及ISETCAD软件,模拟了具有加长LDD结构的高压CMOS器件.器件的击穿电压可以达到30V以上.加长的LDD结构是通过非自对准的源漏注入实现的.LDD区域的长度和该区域的掺杂浓度对器件击穿影响很大.对于不同的工作电压(10-20 V),实验给出了相应的LDD区域长度和该区域的注入剂量.只需要在标准工艺的基础上增加三层掩模版和相应的工艺步骤就能实现低高压工艺的兼容.而且对称结构和非对称结构(具有更大的驱动电流)器件都能实现.与LDMOS或DDDMOS工艺相比,节省了成本,而且所设计的高压器件尺寸较小,有利于集成.     

SOI压力传感器高压失效分析

该文面向基于MEMS技术的SOI压力传感器高压失效问题,以SAW器件为对象开展研究,分别对压力传感器的背腔与正面进行加压,测试两种加压方式下SOI压力传感器的极限耐压值.利用测得的极限耐压值对器件内部应力进行有限元仿真,分析器件耐压失效时的内部最大应力.实验与仿真结果表明,当从背腔加压时,器件失效时的内部应力低于预期值...     

电压加法在直流高压分压器电压系数测量中的应用

用标准分压臂插入法测量直流分压器的误差 ,不确定度难以达到 10 - 4量级。到目前为止 ,高准确度的直流高压分压器的电压系数 ,只能用影响量分项评估方法综合 ,不能给出实际值。应用直流电压加法技术 ,可用计量测试手段实测直流高压分压器在各个工作电压下的误差和不确定度。对 5 0 0kV等级测量结果的不确定度可达到 1 1× 10 - 5。     

高性能图形化SOI功率器件的研制

利用掩膜注氧隔离技术（Masked SIMOX）制备图形化SOI衬底,采用与常规1μmSOI CMOS工艺兼容的工艺流程,制备了图形化SOI LDMOS功率器件。器件的输出特性曲线中未呈现翘曲效应、开态击穿电压高于6V、关态击穿电压达到13V、泄漏电流的量级为10^-8A;截止频率为8GHz;当漏工作电压3．6V,频率为1GHz时,小信号电压增益为6dB。直流和射频电学性能表明,图形化SOI LDMOS结构作为射频功率器件具有较好的开发前景。     

基于SCR的SOI ESD保护器件研究

本文具体分析了体硅SCR(晶闸管)和SOI SCR的抗静电特性,利用软件Sentaurus对埋氧层3μm,顶层硅1.5μm的SOI衬底上的SCR进行了工艺和性能仿真,仿真结果达到了4.5kV的抗静电能力,符合目前人体模型的标准2KV.研究发现,注入剂量(9*13 -8*14cm-2)增加会引起触发电压减小,维持电压升高...     

SOI器件中浮体效应的研究进展

SOI（Silicon On Insulator）器件中氧化埋层的隔离作用带来的浮体效应，将显著地影响器件的性能。本文阐述了浮体效应产生的原因以及它对SOI器件和电路的影响，并从体接触和工艺角度两个方面介绍了目前国际上比较优异的抑制浮体效应的几种典型器件结构。     

纳米 MOSFET/SOI器件新结构

重点介绍器件进入纳米尺度后出现的MOSFET／SOI器件的新结构，如超薄SOI器件、双栅MOSFET、FinFET和应变沟道等SOI器件，并对它们的性能进行了分析。     

氧化铝枪瓷筒高压击穿原因探讨

以本厂生产的大功率速调管为研究对象,用金相和电子显微技术对枪瓷筒高压击穿件和正常件进行对比分析,讨论了产生高压击穿的原因。     

SOI材料研究和应用的新进展及产业化建议

简述了绝缘体上硅(SOI)材料的最新研究动态和国外SOI的最新产业化情况,介绍了国内SOI材料的最新研究进展和应用情况,并对国内SOI材料大规模应用提出了切实的建议.     

全绝缘电压互感器在测量高压电机中的应用

高压电机因其功率大、承受冲击能力强、效率高损耗小等优点,近年来广泛应用于矿山、石油化工和大型船只等需要大动力的领域。然而由于电机的线电压为高电压,无法用普通数字表直接测得,且测试端两端均无法直接接地,给在线测量带来一定的难度。文章通过对比全绝缘电压互感器和普通半绝缘电压互感器,并利用全绝缘电压互感器的优点对高压电机的线电压的测量进行了较为详细的阐述。     

SOI射频集成器件研制

提出了包含射频有源和无源器件的sOI集成结构及工艺方案,在同一SIMOX衬底上制作了射频LDMOS、NMOS、电感、电容、电阻和变容管。核心的LDMOS、NMOS和电感器件均获得了优良的电学特性：0．25μm栅长的LDMOS截止频率和关态击穿电压分别为19．3GHz和16．1V;而0．25μm栅长的NMOS对应参数则为21．3GHz和4．8V;采用开发的局部介质增厚技术后,2nH、5nH、10nH螺旋电感的最大品质因数分别达到了6．5、5．0、4．0,相对于不采用此技术的电感(最大品质因数分别为4．3、3．2、2．3),分别改善了77％,58％,49％。     

State-of-the-art technologies and devices for high-voltage integrated circuits

The current status of high-voltage power semiconductor devices and technologies for high-voltage integrated circuits is reviewed and the new trends in this field are discussed. The paper focuses on the concepts of the novel reduced surface field and state-of-the-art silicon technologies such as high-voltage silicon on insulator, which are expected to play an increasingly important role in power system on-chip manufacturing. Lateral devices such as LDMOSFETs, superjunctions and lateral insulated gate bipolar transistors are discussed. The paper also touches on emerging technologies such as unified MEMS-IC for enhanced breakdown capability and isolation. Finally, an overview of the fierce fight of technology survival in terms of specific on-state resistance against breakdown voltage is given.     

真空高压器件脉冲老炼台的研制

真空高压器件脉冲老炼台由可调直流高压电源、储能器、高压脉冲变压器、高压开关、控制器、真空计、存贮示波器、限流电阻箱、极性转换器、高压击穿判别及高压脉冲分压器等构成，在线测量真空高压器件内的真空度和高压脉冲电压幅度、检测高压击穿状况，高压脉冲电压幅度连续可调、限流电阻和脉冲正负极性自动转换，性能稳定可靠。     

Electrical characteristics of nanoscale NAND silicon-oxide-nitride-oxide-silicon flash memory devices fabricated on SOI substrates

NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length. The device performance of the memory device utilizing the SOI substrate exhibited a smaller subthreshold swing and a larger drain current level in comparison with those on the bulk-Si substrate. These improved electrical characteristices for the SOI devices could be explained by comparing the electric field distribution in a channel region for both devices.     

The fabrication and application of Ni-DNA nanowire-based nanoelectronic devices

DNA is a self-assembled, double stranded natural molecule that can chelate and align nickel ions between its base pairs. The fabrication of a DNA-guided nickel ion chain (Ni-DNA) device was successful, as indicated by the conducting currents exhibiting a Ni ion redox reaction-driven negative differential resistance effect, a property unique to mem-elements (1). The redox state of nickel ions in the Ni-DNA device is programmable by applying an external bias with different polarities and writing times (2). The multiple states of Ni-DNA-based memristive and memcapacitive systems were characterized (3). As such, the development of Ni-DNA nanowire device-based circuits in the near future is proposed.

     

The application of graphene as electrodes in electrical and optical devices

Graphene is a promising next-generation conducting material with the potential to replace traditional electrode materials such as indium tin oxide in electrical and optical devices. It combines several advantageous characteristics including low sheet resistance, high optical transparency and excellent mechanical properties. Recent research has coincided with increased interest in the application of graphene as an electrode material in transistors, light-emitting diodes, solar cells and flexible devices. However, for more practical applications, the performance of devices should be further improved by the engineering of graphene films, such as through their synthesis, transfer and doping. This article reviews several applications of graphene films as electrodes in electrical and optical devices and discusses the essential requirements for applications of graphene films as electrodes.     

Characterization of ultrathin SOI film and application to short channel MOSFETs

In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3?nm. The etch rate is precisely controlled at 0.11???s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15?nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30?nm, featuring state-of-the-art current drive performance.     

RTV胶在空间高压阵二次放电防护技术中的应用研究

室温硫化硅橡胶(RTV胶)可以有效防止空间高压太阳阵产生二次放电事件.本文以地面模拟实验为基础,研究RTV胶在空间高压阵抗二次放电方面的防护作用.实验表明RTV胶明显提高了高压阵二次放电阈值电压;经高能电子辐照后,RTV胶防护样品串间发生耦合放电.通过对经高能电子辐照前后样品RTV胶的红外分析对比,讨论了空间高能电子辐照环境对RTV胶防护二次放电性能的影响.     

穷举法在确定动靶标标准装置参数中的应用

穷举法是根据各个自变量所有可能取值相对应的函数值(输出值)寻找参数特征的一种分析方法。在动靶标标准装置的设计中，尽管其计算公式复杂，但用穷举法还是能比较方便地推算出各参数之间的关系，从而可以合理地设计出满足应用要求的动靶标标准装置。