Temperature control in a rapid thermal processor

Temperature control problems in a rapid thermal processor (RTP) are addressed by using a conventional proportional-integral-derivative (PID) controller and an autoadaptive algorithm. So far, temperature control in most RTP systems has usually been accomplished by using PID controllers. In RTP systems using only classical control schemes, the setting of the control module is a long and complicated task, which often provides optimum results within a limited temperature range. It is shown that adaptive control is less affected by process dynamics     

Thermal modeling of a wafer in a rapid thermal processor

A model, using geometric optics, has been developed to calculate the illumination of a wafer inside a rapid thermal processor. The main parameters of the model are: the processing chamber geometry, the lamp number and location, the reflector characteristics, and the wafer temperature. Each incident light component, i.e., direct or reflected, is identified, its contribution to the illumination of the wafer is calculated through a 3D analytical model, and the corresponding contour maps are depicted. Then, the heat diffusion equation is numerically solved in two dimensions, and thermal maps of a Si wafer are given versus various experimental conditions, such as the effect of patterning the reflectors, of individually adjusting the electrical power applied to each lamp, and the impact of rotating the wafer or using crossed lamp banks. The latter method, while being easy to implement, is shown to give excellent thermal uniformity     

A rapid turnaround design of a high speed VLSI search processor

Performance of relational database systems is a major impediment to their use in many applications. We have designed and implemented a customized RISC processor to accelerate associative search and aggregation operations for relational database systems. Since the processor is programmable and supports many queries concurrently, a system utilizing tens of such processors is capable of handling thousands of complex search requests simultaneously.

While the design of a VLSI programmable processor is a complex process, research prototyping requires a fast turnaround design process. We took advantage of the logic programming paradigm and the silicon compiler technology to explore and simulate architecture alternatives prior to the actual implementation. The prototyping process allowed us to complete the chip design in nine months. The resulting processor, fabricated in 2 Itm CMOS technology, consists of 91,000 transistors, executes over 18 million predicate evaluations per second, and searches database contents at 74 megabytes per second.     

Development of a hexagonal-shaped rapid thermal processor using avertical tube

A new RTP system concept is proposed and demonstrated. The system uses a vertical cylindrical quartz tube, while the wafer is placed horizontally. Linear halogen lamps are arranged in a hexagonal shape, and the hexagonal-shaped lamp groups are stacked vertically. Each lamp group is controlled independently, allowing a temperature difference within ±1.5°C to be achieved over a 6-in wafer in steady state. Oxidation under optimal power condition results in a 1.37% standard deviation for an average oxide thickness of 110.4 Å. The temperature nonuniformity during the transient has been greatly improved by using dynamic control. The convection loss in the system has been evaluated and its radial dependence is found to be smoother in this chamber than in a conventional rectangular chamber. The ray-tracing simulation in three-dimensional space did result in a better comprehension of the optically complex system. The system efficiency has turned out to be lower than in the case of a conventional rectangular chamber. A large portion of the radiation energy is absorbed by the reflectors. There is a strong side heating to the vertical edge of the wafer. Both are due to multiple horizontal reflections of the rays on the reflectors without hitting the wafer. The temperature profiles calculated from the ray-tracing results show an excellent agreement with experiments and confirm the accuracy of the ray-tracing simulation. The main advantages of this new system concept are its excellent temperature uniformity and the good accessibility of the wafer for technological treatments and in situ measurements     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

A contribution to optimal lamp design in rapid thermal processing

Recent studies of wafer temperature control in rapid thermal processing systems have indicated that a multiring circularly symmetric lamp configuration with independent (multivariable) control of the power applied to each ring is likely to be more successful than the earlier lamp design approaches. An important issue in such multiring lamp systems is the optimal shaping of the output heat flux profile (HFP) of each ring to provide maximum controllability of the wafer temperature. In this paper we seek to optimize the ring HFP's via the lamp design parameters: ring positions and widths. We start by determining the heat loss profiles over the wafer surface for a variety of temperature setpoints and processing conditions. In order to maintain temperature uniformity across the wafer at a given setpoint, the lamp system should provide a compensating HFP. The total lamp HFP is the sum of the individual ring HFPs weighted by their respective applied powers. The HFP's are, in turn, functionally dependent on the lamp design parameters and this dependence can be measured through a calibration process. Therefore, the resulting optimization problem reduces to determining the lamp design parameters that result in lamp HFP's which best approximates the collection of the wafer heat loss profiles. Our method provides a practical technique for determining the optimal lamp design parameters     

A novel high-speed fourier-vector processor

A special purpose processor is added to a signal processor, developed at the Lehrstuhl für Nachrichtentechnik, University of Erlangen-Nürnberg for computation of FFT, inverse FFT, and vector operations. The design and implementation of the so-called Fourier-Vector Processor is reported on. The specifications, especially speed and accuracy are investigated. The application for a short-time spectrum analysis using a polyphase filter bank is described as an example.     

A 16-bit specialized processor design

In this paper the ciruit and the design of an experimental 16 bits processor are described. The circuit is used in controller applications between mass storage devices and CPU of mainframes. The chip is fabricated in 2.5μ NMOS technology. This component (45 000 transistors, 35 mm², 40 pins) handles data generated by a CAD tool for real-time control system (PIASTRE).     

Lamp configuration design for rapid thermal processing systems

We have studied lamp configuration design for rapid thermal processing (RTP) systems. We considered a configuration consisting of four concentric circular lamp zones, three of them above the wafer and one circumventing the wafer. We propose a method to determine the geometric parameters, the width, height and radius, of the lamp zones so that the configuration designed has the capacity to achieve a uniform temperature on the wafer. The method is based on a necessary and sufficient condition for uniform temperature tracking and analytic expressions of the view factors. A design example is given in which a least square open-loop control law yields good temperature uniformity     

The design for a Josephson micro-pipelined processor

A novel processor with micro-pipelined architecture is proposed for latch-type Josephson logic devices. The processor is segmented into several operating stages activated by a multi-phase power system. Independent register groups are allocated to each stage in order to support pipeline processing of several instruction streams. This architecture allows building of a fine pipeline pitch processor which is capable of MIMD processing. A 12-bit micro-pipelined Josephson processor, containing an ALU, a multiplier and 16 registers, is described. Driven by a 3-phase AC power system, it is able to process 4 instruction streams simultaneously. A pipeline pitch of 3.3 GHz is expected using conventional Josephson device technology. A 4-bit processor design for 12-bit data length is also discussed     

一款双核处理器的多接口模块设计

介绍了一款基于QorIQ T1系列处理器的多接口模块设计方法,以高性能低功耗双核处理器为平台,以FPGA作为核心控制电路,实现千兆以太网、PCIE、SATA和I2C总线等功能,操作系统可采用VxWorks,性能稳定可靠。     

一种用于可信计算的RISC-V处理器设计

针对我国自主可控处理器的设计需求,文中采用开源RISC-V指令集架构设计了一种适用于可信计算的处理器。处理器内核中指令运算阶段使用5级流水线技术,并采用定向前推技术解决了数据相关问题。仿真阶段使用Modelsim仿真软件对整数指令集进行测试,经验证指令功能正确。借助FPGA开发板,以国产操作系统深度为平台,在50 MHz的时钟频率下处理器能正确运行SM3密码杂凑算法,输出256 bit的杂凑值,并与预存杂凑值进行比对,根据比对结果输出IO控制信号,完成对外部设备的主动控制及度量,达到预期目标。     

Mixed-signal design of a fully parallel fuzzy processor

The authors present a novel architecture for implementing general-purpose fuzzy chips which allows fully-parallel rule processing employing a reduced number of mixed-signal computing blocks and minimum-sized digital memories. The resulting fuzzy processor can interact directly with continuous sensors and actuators and the subsequent digital processing system     

RNS-enabled digital signal processor design

Residue number system (RNS) is explored for implementation of fast digital signal processors with the design of an RNS-based SIMD RISC processor. Simulations conducted on programmable logic show a sustained advantage over commercial chips for a representative set of applications, while prospective results on VLSI technology are also promising     

基于ATCA架构的可重构通信处理机设计

随着数据通信的飞速发展,各种业务需求日益剧增,基于先进电信计算机架构(ATCA)平台,选择可重构的嵌入式系统处理机就显得非常有必要。结合ATCA架构的特点,选择MPC8548E处理器作为处理机,提出了基于1000M以太网和PCI-E数据交互的通信系统模型,设计并实现了一种可重构的通信系统处理机,为基于ATCA架构的电信产品提供了灵活的应用选择。测试结果表明,该处理机无论在电气特性方面,还是在数据的处理能力方面都达到了业内相对领先的地步。     

Parallel VLSI design for a real-time video-impulse noise-reduction processor

High-quality televisions (TVs) such as improved digital TV, enhanced TV, and high-definition TV have become popular in recent years. However, impulse noise affects TV broadcasts. This paper proposes an efficient noise-removal algorithm using an adaptive digital signal-processing approach. Simulations have demonstrated that the new adaptive algorithm could efficiently reduce impulse noise even in highly corrupted images. In order to achieve real-time implementation, a cost-effective architecture is proposed using a parallel structure and pipelined processing. The proposed processor can achieve the throughput rate of 45M pixels/s using only 4k gates and two line buffers. Unlike median-filtering chips, this processor provides better filtering quality and its circuit is much less complex.     

一种雷达信号处理机的软件设计

结合某雷达信号处理机研制项目,对该雷达信号处理机的脉冲压缩、动目标显示和动目标检测、恒虚警处理等软件进行设计。论文首先回顾了该处理机用到的几种雷达信号处理方法：线性调频信号的脉冲压缩、基于一次相消器和二次相消器的动目标显示、通过窄带多普勒滤波器组的动目标检测处理、恒虚警检测等方面的工作原理和实现方式。根据信号处理机硬件平台设计了相关的信号处理软件,并实现上述信号处理功能。     

A global model for rapid thermal processors

A simple model for the components that make up a rapid thermal processing system is given. These components are the furnace, the pyrometer used to measure temperature, and the control system that utilizes the pyrometer measurement to control the power to the lamps. The models for each of the components are integrated in a numerical code to give a computer simulation of the complete furnace operation. The simulation can be used to investigate the interaction of the furnace, temperature-sensing technique, and the control system. Therefore, the interplay of heat transfer (furnace) properties, optical (pyrometer) parameters, and control gains can be studied. The objective is to define variability in wafer temperature as process parameters change. The following three applications of the model are included: (1) a simulation of open-loop operation; (2) a simulation of the ramp up and subsequent operation with a step change in wafer optical properties; and (3) a simulation of the rapid thermal chemical vapor deposition of polysilicon on silicon oxide which demonstrates the applicability model for actual processes. A technique for correction of pyrometer output to improve temperature control is also presented