The application of loss-free resistors in power processing circuits

Applications of loss-free elements with resistive characteristics in power processing systems are discussed. The synthesis of this kind of element is based on the control of a two port which has a transformer or gyrator matrix. Both of the controlled two ports can be realized by means of switched mode circuits. The loss-free resistor can be applied to the stabilization of unstable systems, for damping oscillatory waveforms, and balancing of power flow in AC-DC conversion systems. This kind of element has been applied to the stabilization of a gas laser system. It replaced a conventional resistive element which was applied for this purpose     

Modeling non-linear power electronic circuits with thetransmission-line modeling technique

This paper describes a nonlinear transmission line modeling technique that can be employed to model power electronic circuits. The nonlinearities that can be dealt with also include the switching action of the power devices as well as the nonlinear behavior of saturable inductors and multilayer capacitors. With this new nonlinear technique, the transmission line modeling technique can now be used as a generalized discrete-time modeling tool for power electronic circuits. The nonlinear technique is demonstrated in two examples and the simulations are found to be satisfactory     

Fast modeling of core switching noise on distributed LRC power gridin ULSI circuits

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0±5%. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted     

Two-dimensional thermal modeling of power monolithic microwaveintegrated circuits (MMICs)

Numerical simulations of the two-dimensional temperature distribution for a typical GaAs MMIC circuit were conducted in order to understand the heat conduction process of the circuit chip and to provide temperature information for device reliability analysis. The method used is to solve the two-dimensional heat conduction equation with a control-volume-based finite difference scheme. In particular, the effects of the power dissipation and the ambient temperature are examined, and the criterion for the worst operating environment is discussed in terms of the allowed highest device junction temperature     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

基于智慧电源架构的DC-DC并联研究

为了解决多个模块电源协同工作的问题,提出了智慧电源的概念和架构。智慧电源包含三大关键技术:模块电源技术、实时局域网技术和智能控制技术。对这三大技术进行分析,基于智慧电源的架构,设计一套由3个DC-DC电路组成的并联运行系统,并进行了实验,成功实现了电流均流、效率优化等控制。理论分析和实验表明,智慧电源是一种解决模块电源协同工作问题的有效的、通用的思路和方法。     

A simple metal-semiconductor substructure for the advanced thermo-mechanical numerical modeling of the power integrated circuits

The metallization of double-diffused metal-oxide semiconductor (DMOS) power devices, which operate under fast thermal cycling (FTC), undergoes thermal induced plastic metal deformation (TPMD). The design of the metallization has a significant impact on the device lifetime and thus requires a thorough understanding of the temperature, stress and strain distribution. A simple three-dimensional (3D) transistor substructure which is commonly found in various high integration Bipolar-CMOS-DMOS (BCD) technologies is analysed. The thermomechanical behaviour is studied with the finite element method (FEM) for investigation of two potential failure mechanisms: delamination of power metal and accumulation of plastic deformation in signal metallization layer (which leads to inter-metal dielectric cracking). These failure mechanisms are analysed on two versions of the structure: the first one has only signal and power metal lines and the second one has vias, in addition to the signal and power metal lines. The target of the paper is to propose an efficient finite element analysis (FEA) model that can be used for a qualitative assessment of thermo-mechanical phenomena in the metal system of high integration BCD technologies.     

Maximum power point tracker based on maximum power point resistance modeling

This paper presents a new, simple, accurate, and inexpensive practical methodology and experimental solution for the modeling of conventional (domestic and commercial facilities) photovoltaic generators (PVG), so that they can work at their maximum power point (MPP). The PVG may be a panel, an array of panels, or a photovoltaic field. As a starting restriction (actual) it has to be assumed that it is not possible to isolate the PVG variables dependence (mainly current, voltage, and hence power) with solar radiation and temperature, because they are highly correlated. This methodology proposes the modeling facility on its MPP by its MPP resistance (R_MPP = V_MPP/I_MPP), being V_MPP and I_MPP the voltage and current of the PVG, respectively, at its MPP. The analysis shows, by simulation first and then experimentally, that R_MPP does not present significant temperature dependencies, at least in the usual range. This important result allows us to model the PVG only in terms of solar radiation. From a set of experimental data, different models to estimate R_MPP are proposed. The obtained results are very accurate. These models allow an immediate practical application that it is also developed in the paper: MPP tracker (MPPT) design by the calculation of the DC/DC converter duty cycle which places the PVG at its MPP directly and continuously. This new methodology and experimental system has been registered in the Spanish Patent and Trademark Office with the number P201530352. Copyright © 2015 John Wiley & Sons, Ltd.     

Stochastic interconnect modeling, power trends, and performancecharacterization of 3-D circuits

Three-dimensional (3-D) technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of two dimensions (2-D), which are widely considered as the barriers to continued performance gains in future technology generations. Thus, understanding the interconnect and its related issues, such as the impact on circuit performance, is key to 3-D circuit applications. In this paper, we present a stochastic 3-D interconnect model and study the impact of 3-D integration on circuit performance and power consumption. To model 3-D interconnect, we divide 3-D wires into two parts (horizontal wires and vertical wires) and derive their stochastic distributions. Based on those distributions, we estimate the delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double or even triple) than 2-D     

基于GSAA算法的组合电路最大功耗估计方法

最大功耗估计问题是一个NP难题。提出的方法利用遗传模拟退火算法(GSAA)在整个解空间快速搜索问题的最优解，实现组合电路最大功耗的快速、精确估计。仿真结果表明，提出的方法比基于遗传算法(GA)的估计方法在估算精度和收敛速度上都有提高，适合于大规模组合电路最大功耗的估计。     

基于物理结构的GaN HEMTs小信号等效电路的精确建模方法研究

为了有效地表征GaN HEMTs在微波频段下的电学特性,研究了其高频等效电路的精确建模方法。基于GaN HEMTs器件的本征物理结构,综合考虑器件在制版过程中由电极和通孔所带来的寄生特性,描述了一种具有26个详细参数网络的小信号等效电路模型。此模型考虑了器件在工作环境下所受到的集肤效应,同时通过对小信号等效电路进行双端口网络参数分析,推导了其准静态近似的微波等效电路参数直接提取的简化算法,最终通过ADS仿真平台将所建模型和传统模型的S参数模拟结果与实测数据的一致性进行对比,验证了小信号等效电路模型的精确性与参数提取算法的有效性。     

Ultra low power DG FinFET based voltage controlled oscillator circuits

Voltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations.     

Canonical space-time processing for wireless communications

A canonical space-time characterization of mobile wireless channels is introduced in terms of a fixed basis that is independent of the true channel parameters The basis captures the essential degrees of freedom in the received signal using discrete multipath delays, Doppler shifts, and directions of arrival (DOA). The canonical representation provides a robust representation of the propagation dynamics and eliminates the need for estimating delay, Doppler and DOA parameters of different multipaths, Furthermore, it furnishes a natural framework for designing low-complexity space-time receivers. Single-user receivers based on the canonical channel representation are developed and analyzed, It is demonstrated that the resulting canonical space-time receivers deliver near-optimal performance at substantially reduced complexity compared to existing designs.     

Switched-capacitor power electronics circuits

One of the main orientations in power electronics in the last decade has been the development of switching-mode converters without inductors and transformers. Light weight, small size and high power density are the result of using only switches and capacitors in the power stage of these converters. Thus, they serve as ideal power supplies for mobile electronic systems (e.g. cellular phones, personal digital assistants, and so forth). Switched-capacitor (SC) converters, with their large voltage conversion ratio, promise to be a response to such challenges of the 21st century as high-efficiency converters with low EMI emissions and the ability to realize steep step-down of the voltage (to 3 V or even a smaller supply voltage for integrated circuits) or steep step-up of the voltage for automotive industry or Internet services in the telecom industry. This paper is a tutorial of the main results in SC-converter research and design     

Canonical piecewise—Linear analysis for nonlinear DC fault circuits

This paper uses canonical piecewise—linear analysis method to analyze nonlinear DC fault circuits and solve for the values of the test port voltages which are selected beforehand. The method needs less memory storages, obtains the results in finite steps and has high efficiency in computation. It can be applied to the circuits containing multiport nonlinear elements. It is a good method of pre—test analysis for fault circuits in simulation—before—test aproach in analogue circuit diagnosis.     

Geometric modeling of nonlinear RLC circuits

In this paper, the dynamics of nonlinear RLC circuits including independent and controlled voltage or current sources is described using the Brayton-Moser equations. The underlying geometric structure is highlighted and it is shown that the Brayton-Moser equations can be written as a dynamical system with respect to a noncanonical Dirac structure. The state variables are inductor currents and capacitor voltages. The formalism can be extended to include circuits with elements in excess, as well as general noncomplete circuits. Relations with the Hamiltonian formulation of nonlinear electrical circuits are clearly pointed out.     

Behavioral modeling of RF power amplifiers based on pruned volterra series

Behavioral modeling techniques provide a convenient and efficient means to predict system-level performance without the computational complexity of full circuit simulation or physics-level analysis of nonlinear systems, thereby significantly speeding up the analysis process. General Volterra series based models have been successfully applied for radio frequency (RF) power amplifier (PA) behavioral modeling, but their high complexity tends to limit their applications to "weakly" nonlinear systems. To model a PA with strong nonlinearities and long memory effects, for example, the general Volterra model involves a great number of coefficients. In this letter, we propose a new simplified Volterra series based model for RF power amplifiers by employing a "near-diagonality" pruning algorithm to remove the coefficients which are very small, or else not sensitive to the output error, therefore dramatically reducing the complexity of the behavioral model.     

Nonlinear modeling and processing of speech based on sums of AM-FMformant models

We describe a new statistical approach based on nonlinear filtering ideas for decomposing signals that are modeled as a sum of jointly amplitude- and frequency-modulated cosines, where each cosine has a slowly varying center frequency and the sum of terms is observed in additive noise. This is an alternative approach to methods based on deterministic models such as the Kaiser-Teager (see Proc. IEEE ICASSP-93, vol.III, p.149 and IEEE Trans. Acoust., Speech, Signal Processing, vol.28, no.5, pp. 599, 1980) energy operator. The Cramer-Rao bound for the resulting statistical estimation problem is computed. A practical nonlinear filter, an extended Kalman filter, is described. We demonstrate the ideas on a variety of speech problems     

基于Hadoop的光伏发电大数据分析系统设计

光伏发电系统的发电效率和光伏组件的材料、组件安装的倾斜角度及组件功率等因素有密切关系,为了科学地研究这些因素对发电量的实际影响,文中选择使用Hadoop大数据分析工具,它由HDFS分布式文件系统和MapReduce数据处理框架两大核心部件组成,通过它提供的强大的分布式数据处理能力,高效快捷地分析光伏发电系统运行中所产生的各种数据。实验表明该系统能够有效地完成光伏数据处理分析,从海量数据中挖掘到有用信息,对光伏发电发展提供重要助力。