The application of loss-free resistors in power processing circuits

Applications of loss-free elements with resistive characteristics in power processing systems are discussed. The synthesis of this kind of element is based on the control of a two port which has a transformer or gyrator matrix. Both of the controlled two ports can be realized by means of switched mode circuits. The loss-free resistor can be applied to the stabilization of unstable systems, for damping oscillatory waveforms, and balancing of power flow in AC-DC conversion systems. This kind of element has been applied to the stabilization of a gas laser system. It replaced a conventional resistive element which was applied for this purpose     

Modeling non-linear power electronic circuits with thetransmission-line modeling technique

This paper describes a nonlinear transmission line modeling technique that can be employed to model power electronic circuits. The nonlinearities that can be dealt with also include the switching action of the power devices as well as the nonlinear behavior of saturable inductors and multilayer capacitors. With this new nonlinear technique, the transmission line modeling technique can now be used as a generalized discrete-time modeling tool for power electronic circuits. The nonlinear technique is demonstrated in two examples and the simulations are found to be satisfactory     

Fast modeling of core switching noise on distributed LRC power gridin ULSI circuits

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0±5%. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted     

Two-dimensional thermal modeling of power monolithic microwaveintegrated circuits (MMICs)

Numerical simulations of the two-dimensional temperature distribution for a typical GaAs MMIC circuit were conducted in order to understand the heat conduction process of the circuit chip and to provide temperature information for device reliability analysis. The method used is to solve the two-dimensional heat conduction equation with a control-volume-based finite difference scheme. In particular, the effects of the power dissipation and the ambient temperature are examined, and the criterion for the worst operating environment is discussed in terms of the allowed highest device junction temperature     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

基于智慧电源架构的DC-DC并联研究

为了解决多个模块电源协同工作的问题,提出了智慧电源的概念和架构。智慧电源包含三大关键技术:模块电源技术、实时局域网技术和智能控制技术。对这三大技术进行分析,基于智慧电源的架构,设计一套由3个DC-DC电路组成的并联运行系统,并进行了实验,成功实现了电流均流、效率优化等控制。理论分析和实验表明,智慧电源是一种解决模块电源协同工作问题的有效的、通用的思路和方法。     

Stochastic interconnect modeling, power trends, and performancecharacterization of 3-D circuits

Three-dimensional (3-D) technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of two dimensions (2-D), which are widely considered as the barriers to continued performance gains in future technology generations. Thus, understanding the interconnect and its related issues, such as the impact on circuit performance, is key to 3-D circuit applications. In this paper, we present a stochastic 3-D interconnect model and study the impact of 3-D integration on circuit performance and power consumption. To model 3-D interconnect, we divide 3-D wires into two parts (horizontal wires and vertical wires) and derive their stochastic distributions. Based on those distributions, we estimate the delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double or even triple) than 2-D     

基于GSAA算法的组合电路最大功耗估计方法

最大功耗估计问题是一个NP难题。提出的方法利用遗传模拟退火算法(GSAA)在整个解空间快速搜索问题的最优解，实现组合电路最大功耗的快速、精确估计。仿真结果表明，提出的方法比基于遗传算法(GA)的估计方法在估算精度和收敛速度上都有提高，适合于大规模组合电路最大功耗的估计。     

Behavioral modeling of RF power amplifiers based on pruned volterra series

Behavioral modeling techniques provide a convenient and efficient means to predict system-level performance without the computational complexity of full circuit simulation or physics-level analysis of nonlinear systems, thereby significantly speeding up the analysis process. General Volterra series based models have been successfully applied for radio frequency (RF) power amplifier (PA) behavioral modeling, but their high complexity tends to limit their applications to "weakly" nonlinear systems. To model a PA with strong nonlinearities and long memory effects, for example, the general Volterra model involves a great number of coefficients. In this letter, we propose a new simplified Volterra series based model for RF power amplifiers by employing a "near-diagonality" pruning algorithm to remove the coefficients which are very small, or else not sensitive to the output error, therefore dramatically reducing the complexity of the behavioral model.     

Canonical space-time processing for wireless communications

A canonical space-time characterization of mobile wireless channels is introduced in terms of a fixed basis that is independent of the true channel parameters The basis captures the essential degrees of freedom in the received signal using discrete multipath delays, Doppler shifts, and directions of arrival (DOA). The canonical representation provides a robust representation of the propagation dynamics and eliminates the need for estimating delay, Doppler and DOA parameters of different multipaths, Furthermore, it furnishes a natural framework for designing low-complexity space-time receivers. Single-user receivers based on the canonical channel representation are developed and analyzed, It is demonstrated that the resulting canonical space-time receivers deliver near-optimal performance at substantially reduced complexity compared to existing designs.     

Switched-capacitor power electronics circuits

One of the main orientations in power electronics in the last decade has been the development of switching-mode converters without inductors and transformers. Light weight, small size and high power density are the result of using only switches and capacitors in the power stage of these converters. Thus, they serve as ideal power supplies for mobile electronic systems (e.g. cellular phones, personal digital assistants, and so forth). Switched-capacitor (SC) converters, with their large voltage conversion ratio, promise to be a response to such challenges of the 21st century as high-efficiency converters with low EMI emissions and the ability to realize steep step-down of the voltage (to 3 V or even a smaller supply voltage for integrated circuits) or steep step-up of the voltage for automotive industry or Internet services in the telecom industry. This paper is a tutorial of the main results in SC-converter research and design     

基于Hadoop的光伏发电大数据分析系统设计

光伏发电系统的发电效率和光伏组件的材料、组件安装的倾斜角度及组件功率等因素有密切关系,为了科学地研究这些因素对发电量的实际影响,文中选择使用Hadoop大数据分析工具,它由HDFS分布式文件系统和MapReduce数据处理框架两大核心部件组成,通过它提供的强大的分布式数据处理能力,高效快捷地分析光伏发电系统运行中所产生的各种数据。实验表明该系统能够有效地完成光伏数据处理分析,从海量数据中挖掘到有用信息,对光伏发电发展提供重要助力。     

Nonlinear modeling and processing of speech based on sums of AM-FMformant models

We describe a new statistical approach based on nonlinear filtering ideas for decomposing signals that are modeled as a sum of jointly amplitude- and frequency-modulated cosines, where each cosine has a slowly varying center frequency and the sum of terms is observed in additive noise. This is an alternative approach to methods based on deterministic models such as the Kaiser-Teager (see Proc. IEEE ICASSP-93, vol.III, p.149 and IEEE Trans. Acoust., Speech, Signal Processing, vol.28, no.5, pp. 599, 1980) energy operator. The Cramer-Rao bound for the resulting statistical estimation problem is computed. A practical nonlinear filter, an extended Kalman filter, is described. We demonstrate the ideas on a variety of speech problems     

Logical effort based dynamic power estimation and optimization of static CMOS circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates, sizes and processes, the developed model shows a good agreement with Hspice simulations using BSIM3v3 and BSIM4 models for UMC 0.13 μm and Predictive high-k 45 nm processes, respectively. The average error introduced by the model for the considered scenarios is about 3.1%. Depending on the normalized switching power model, two power optimization techniques have been proposed in this paper. The first deals with transistor sizing problem and presents a scheme to size transistors according to a specific design goal. The second technique relies on the joint transistor sizing and supply voltage scaling for reducing the switching power dissipation under specific delay requirements. This technique exhibits superiority over the first for the considered technology processes: UMC 0.13 μm and the Predictive high-k 45 nm.     

Geometric modeling of nonlinear RLC circuits

In this paper, the dynamics of nonlinear RLC circuits including independent and controlled voltage or current sources is described using the Brayton-Moser equations. The underlying geometric structure is highlighted and it is shown that the Brayton-Moser equations can be written as a dynamical system with respect to a noncanonical Dirac structure. The state variables are inductor currents and capacitor voltages. The formalism can be extended to include circuits with elements in excess, as well as general noncomplete circuits. Relations with the Hamiltonian formulation of nonlinear electrical circuits are clearly pointed out.     

Reliability modeling on a MOSFET power package based on embedded die technology

Embedding of discrete semiconductors into substrates has the advantages of achieving high degree of miniaturization, good electrical performance and possible low cost. A MOSFET power package based on the embedded die technology was developed and the demonstrators were built. To reduce cost and time-to-market, thermo-mechanical virtual prototyping is applied to support the package development. 2D and 3D parametric FE models were established to conduct numerical simulations to investigate the thermo-mechanical reliability performance under packaging processes and test conditions. The package design and material variations, such as the thicknesses of the Cu layer and the resin in the RCC foil, the Bond Line Thickness (BLT), the thickness and material properties of prepreg, via dimensions and via-filling, were included in the parametric models. The root cause for die cracking, delamination between the interface die/RCC foil, and cracking of Cu vias were analyzed based on the simulation results. Verification of the modeling results was conducted through comparison with the test results. The results indicate that the prediction from the FE modeling matches reasonably well with the test results.     

A novel flash EEPROM cell based on trench technology forintegration within power integrated circuits

A flash EEPROM suitable for integration within power integrated circuits (PIC's) is presented. The EEPROM cell uses a trench floating gate to give a large gate charge while using no more silicon area than a conventional flash EEPROM cell. The cell shows good immunity against the induced disturbance voltages which are present in a PIC, and the storage lifetime is greater than ten years at a reading voltage of V_D=2.2 V     

基于多值开关-信号理论的三值低功耗动态异或/同或电路设计

通过对多值开关-信号理论(Multiple-value Switch-signal Theory,MST)和三值异或/同或(XOR/XNOR)电路工作原理的研究,本文提出具有预充电功能的三值低功耗动态异或/同或电路的设计方案.该方案通过在预充电阶段将输出信号预充至逻辑值"1",避免电路级联电荷再分配;采用开关级逻辑结构消除输出悬空态,保证输出信号具有完整的逻辑摆幅和高噪声容限.PSPCIE模拟验证所设计电路逻辑功能正确,低功耗特性明显.