Bit-error-rate performance of intra-chip wireless interconnect systems

This Letter evaluates the bit-error rate (BER) performance of a coherent binary phase-shift keying interconnect system operating on an intra-chip wireless channel at 15 GHz. Results show that the system performance degrades with the separation distance and the data rate. A high data rate at 2 Gb/s with a low BER<10/sup -5/ over the entire chip of size 20 /spl times/ 20 mm can be achieved with the transmitted power of 10 dBm.     

Stress-voiding in tungsten-plug interconnect systems induced byhigh-temperature processing

We describe the sensitivity of sub-micron via integrity to high-temperature processing following via etch. It has been observed that thermal expansion of Al into the via hole, before tungsten deposition, may result in the fabrication of a deformed tungsten plug. Our results indicate that relaxation of the Al can give rise to stress-void formation under the tungsten plug. This may manifest itself either during electromigration stress or high-temperature storage. This mechanism represents a new reliability hazard for a tungsten-plug interconnect system     

A monolithic GaAs receiver for optical interconnect systems

A monolithic GaAs optical receiver which includes a photodetector and preamplifier was designed and fabricated using a common 1.0-μm GaAs MESFET technology. The optical receiver operates at the data rate of 1 Gb/s. The transimpedance value can be continuously tuned from 1 to 10 kΩ. The metal-semiconductor-metal photodiode shows a 35% efficiency. Several design factors are considered to achieve high-bandwidth and low-noise operation. An array of the integrated receivers can be compactly implemented in a single chip for high-speed interconnection networks and photonic signal processing     

Accurate on-chip interconnect evaluation: a time-domain technique

This paper describes an on-chip sampling and measurement technique for accurate (<15 ps) evaluation of interconnect delays and coupled noise. We have used this nonintrusive time-domain technique to extract in situ driver/receiver waveforms, propagation delays, and coupled noise in 120 interconnect structures. The effects studied include multiple AC returns through active devices, gridded planes on adjacent layers, via impedances, variable driver impedances, and noise in bus structures. The results provide a comprehensive evaluation of interconnect delays and noise in a 1.8 V, 0.25 μm process     

Performance evaluation of DS-CDMA systems on multipath propagationchannels with multilevel spreading sequences and RAKE receivers

Performance of small-cell wireless direct sequence code-division multiple access (DS-CDMA) systems with multilevel spreading sequences is investigated. An analytical methodology to evaluate both outage probability and mean bit error probability is presented; and its results are compared to those obtained with a semianalytical Monte Carlo based approach. Multipath propagation, the exact correlation properties of spreading codes, and both the simple correlator and RAKE receivers are taken into account in the analysis, which is oriented to asynchronous and synchronous environments. The spreading sequences investigated include multilevel sequences with complex isomorphic mapping, as well as some well-known two-level sequences. The numerical results show the impact of multilevel sequences on system performance, the improvements found in the absence of multiple access interference by using them rather than binary sequences, and the agreement between analytical and semianalytical evaluation     

A new electromigration testing technique for rapid statistical evaluation of interconnect technology

We describe a test structure and a testing technique that allows simultaneous stressing of 50 or more parallel thin film lines of the same width. This technique allows determination of the mean time to electromigration-induced failure and the deviation in the time to failure in a single test. This technique allows more rapid statistical evaluation of new or modified interconnect technologies.     

An evaluation of fast wafer level test methods for interconnect reliability control

A number of fast wafer level test methods exist for interconnect reliability evaluation. The relative abilities of three such methods to predict the quality and reliability of the interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are compared with package level Median Time to Failure (MTF) results. The Isothermal test method combined with SWEAT-type test structures is shown to be the most suitable combination for interconnect reliability detection and control over very short times.     

Advanced experimental and computational tools for robust evaluation of on-chip interconnect reliability

Two technologies are introduced that, together, provide a platform for robust evaluation of interconnect reliability. One is the DISMAP technology, which provides plots of the displacement and strain fields of cross-sectioned interconnect structures under various loading conditions. Measurements provided by DISMAP reveal how multilevel-interconnect structures interact structurally, for example what type of strain fields exist during thermal cycling. A complimentary technology, known as probabilistic analysis, is also described and applied using the NESSUS software. Probabilistic analysis combines statistical uncertainty with physics-based models to predict the probability of failure and also to reveal the relative importance of the various uncertainties associated with interconnect manufacturing. By comparing the predictions of physical models to DISMAP measurements, the validity of those models are evaluated.     

Adaptive rate DS-CDMA systems using variable spreading factors

In this contribution, adaptive rate transmissions are investigated in the context of direct-sequence code-division multiple-access (DS-CDMA) systems using variable spreading factors (VSFs). In the context of the recently established family of adaptive rate-transmission schemes, the transmission rate is typically adapted in response to the channel's fading-induced quality fluctuation. By contrast, in this contribution the transmission rate is adapted in response to the multiuser interference fluctuations encountered. We present the philosophy of the proposed adaptive rate-transmission scheme and analyze the effective throughput as well as the achievable bit error rate (BER) performance, when communicating over additive white Gaussian noise channels. Our study shows that by employing the proposed VSF-assisted adaptive rate-transmission scheme, the effective throughput may be increased by up to 40%, when compared to that of DS-CDMA systems using constant spreading factors. This increased throughput is achieved without wasting power, without imposing extra interference upon other users, and without increasing the BER.     

Fast statistical delay evaluation of RC interconnect in the presence of process variations

Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closed-form expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology.     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

考虑工艺波动的快速RC互连延时统计计算

本文提出了一种考虑工艺波动影响的计算延时和过渡时间的快速统计模型。模型中使用优化的二阶模型描述工艺波动的影响,使用了闭合表达式来表示相关工艺参数和工艺波动影响下的延时和过渡时间之间的关系。仿真实验表明：提出的模型和传统算法有相似的精度和相似的统计特性,而计算效率大大高于基于HSPICE的模特卡罗分析和传统方法。     

Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems

Continuous scaling of conventional hard-wired metal interconnects into deep sub-micrometer region (DSM) has resulted in significant performance degradation in terms of delay, crosstalk noise, higher power dissipation, and decreased tolerance to noise. Besides, communication-centric nature of system-on-chip (SOC) networks requires efficient intra- and inter-chip interconnect technologies. Radio-frequency (RF)/wireless interconnects promise to be the best alternative to metal interconnects as they are compatible with current CMOS-technology, and they also provide higher data rate and bi-directional multi I/O transmissions. This paper evaluates the system bit-error-rate (BER) performance with the application of fault-tolerance capability using linear error-control codes (ECCs) within chip (intra-chip) RF/wireless interconnect systems. It also evaluates the utility of ECCs by considering energy consumed in ECC encoding-decoding vis-à-vis the energy saved due to coding gain by calculating the critical distance (d_cr). The results indicate that for a certain range of received signal-to-noise ratio (SNR), application of ECC improves the BER performance of the RF/wireless interconnect system. It is also shown that d_cr drops to 0.7 mm at 18 GHz.     

铜互连制程中酸碱性抛光液的平坦化效果评估

We observed and analyzed the acid and HEBUT alkaline of Cu chemical mechanical polishing(CMP)slurry to evaluate their effects. Material analysis has shown that the planarity surfaces and the removal rate of alkaline slurry are better than the acid slurry during metal CMP processes. The global surface roughness and the small-scale surface roughness by 1010 m2 of copper film polished by the SVTC slurry are 1.127 nm and2.49 nm. However, it is found that the surface roughnesses of copper films polished by the HEBUT slurry are 0.728 nm and 0.215 nm. All other things being equal, the remaining step heights of copper films polished by the SVTC slurry and HEBUT slurry are respectively 150 nm and 50 nm. At the end of the polishing process, the dishing heights of the HEBUT slurry and the SVTC slurry are approximately both 30 nm, the erosion heights of the HEBUT slurry and the SVTC slurry are approximately both 20 nm. The surface states of the copper film after CMP are tested,and the AFM results of two samples are obviously seen. The surface polished by SVTC slurry shows many spikes.This indicates that the HEBUT alkaline slurry is promising for inter-level dielectric(ILD) applications in ultra large-scale integrated circuits(ULSI) technology.     

A two-layer spreading code scheme for dual-rate DS-CDMA systems

This letter considers multiuser detection in variable-spreading-length multi-rate direct-sequence code-division multiple-access systems. A two-layer spreading (TLS) code scheme is proposed which facilitates the low-complexity adaptive implementation of linear minimum mean-square error multiuser receivers in a dual-rate system. It is demonstrated via large system analysis and simulation that imposing a TLS structure does not incur loss in terms of the output signal-to-interference ratio performance.     

Multicarrier CDMA systems using time-domain and frequency-domain spreading codes

For wideband code-division multiple-access systems, the paper introduces a multicarrier modulation scheme that performs the spreading simultaneously in the time and frequency domains. This scheme attains higher flexibility and spectrum efficiency because system parameters can be selected at will. The performance is compared with that of a single carrier RAKE system by calculating the probability of error over a frequency-selective Rayleigh fading channel. The proposed scheme outperforms the single carrier RAKE system if the system parameters are selected properly for given conditions, such as bandwidth and delay spread.     

The isocurrent test: A promising tool for wafer-level evaluation of the interconnect reliability

A highly accelerated wafer-level electromigration test, the isocurrent test, is presented. A constant high current is used to give both the current and temperature stress to a 4-point resistor with a bonding pad layout which minimizes temperature gradients. The test is used to evaluate unpassivated Al---Cu and passivated Al---Si---Cu lines of different line width. Log normal failure distributions are obtained and the line width dependence of the MTTF and DTTF is similar to that observed in classical electromigration tests. A storage test at 250 °C clearly deteriorates the lifetime of 0.5 and 0.7 μm passivated lines. This is probably due to stress induced void formation.     

Pulsed wave interconnect

Pulsed wave interconnect is proposed for global interconnect applications. Signals are represented by localized wave-packets that propagate along the interconnect lines at the local speed of light to trigger the receivers. Energy consumption is reduced through charging up only part of the interconnect lines and using the voltage doubling property of the receiver gate capacitances. In a 0.18-/spl mu/m CMOS technology case study, SPICE simulations show that pulsed wave interconnect can save up to 50% of energy and /spl sim/30% of chip area in comparison with the repeater insertion method. A proposed signal splitting structure provides reasonable isolations between different receivers. Measured S-parameters of 3.8-mm interconnect lines fabricated through CMOS foundry showed that the distortion and attenuation of a pico second signal are much less serious than the theoretical predictions. Pulsed wave interconnect also enables time division application of a single line to boost its bit rate capacity. The use of nonlinear transmission lines (NLTL) is also proposed to overcome pulse broadening and attenuation caused by dispersion and frequency-dependent losses. Pulsed waves on an NLTL may be generated, transmitted, split and detected with components realizable in bulk and SOI CMOS technologies. Tapered NLTL can be used for pulse compression. NLTL edge sharpening abilities may be applicable for signal rise time control.     

MB-OFDM-UWB系统基于时域扩展的盲频率跟踪算法

对多频带正交频分复用超宽带系统同步技术进行研究,提出一种基于时域扩展技术（TDS）的盲载波频偏（CFO）跟踪算法。利用数据符号与其时域扩展符号的特殊映射关系,在时域和频域分别推导出残余载波频偏的盲估计公式,并构建相应的时频跟踪环路。仿真结果表明,该盲算法具有比导频辅助法更优的跟踪性能。10dB信噪比下,基于TDS进行时频跟踪的残余CFO均方根误差均达到2×10?4,系统误比特率可达10?6数量级。     

Chip-delay locked matched filter for DS-CDMA systems using longsequence spreading

This paper considers an improved single-user detection technique for asynchronous direct-sequence code-division multiple-access (DS-CDMA) systems using long sequence spreading (random-CDMA) Most of the known detection schemes for DS-CDMA suffer from either poor performance under power-imbalance (near-far like) conditions, excessive complexity, or incompatibility with systems employing long sequence spreading. To address these problems, this paper considers a signal-to-noise ratio maximizing linear time-invariant filter for one-shot bit symbol detection exploiting some information about the interferers. This filter, referred to as the chip-delay locked matched filter (CLMF), exploits the cyclostationarity in multiple-access interference, and it can offer good near-far resistance while remaining suitable for systems with long sequence spreading. The CLMF requires knowledge of interferers chip delays and signal powers; however, knowledge of their pseudonoise sequences is unnecessary. This paper also demonstrates the improvement in performances offered by the CLMF over other single-user receivers such as the conventional matched filter and noise-whitening matched filter performance is evaluated in terms of probability of outage for single-rate and dual-rate DS-CDMA systems using bandwidth-efficient chip pulses, over a single-path additive white Gaussian noise channel. Errors in the interferer chip delay estimates degrade the CLMF performance. However, if the root-mean-square value of these errors is less than 5% of the chip interval, then this degradation is small