集成电路中MOS管导通电阻测量方法

MOS管是一种常见的半导体功率器件,随着半导体产业的不断发展和进步,MOS管的各方面性能也得到大幅度的提高,被广泛应用于开关电源、节能灯、电源转换和电源控制等领域。在功率电路中,MOS作为一种多子功率开关器件,其导通电阻是至关重要的参数之一,会影响到应用电路的稳定性和功耗。因此在集成电路测试中对于MOS管导通电阻的精确测量显得尤为重要。对于MOS管导通电阻的测量做了详细分析,并介绍了两种可以准确测量MOS管导通电阻的方法。     

双功率场效应管(MOSFET)用作锂离子安全开关

n沟道器件使用一种独特的公共漏极设计以使导通电阻最小为能够用作铿离子电池封装的安全开关,TSSOPS脚封装的Si6968DQ双n沟道功率MOS场效应管把本公司     

功率场效应晶体管晶圆超薄磨片工艺开发

晶圆超薄磨片工艺是为减小功率开关管导通电阻,工艺中存在超薄晶圆磨片后转运过程中破片及超薄晶圆背面蒸镀金属等问题.现有的晶圆磨片的一般厚度为200μm,超薄磨片的目标是100μm.本研究采用同一批次晶圆,分批,2片超薄研磨,其他采用正常工艺减薄,封装测试条件相同.对比封装测试完毕的器件的导通电阻,超薄研磨器件的导通电阻减小约10%.     

功率MOS器件

本文介绍新近功率MOS场效应晶体管的主要结构和电学性能。为了提高MOS晶体管的电流和电压容量,首先得论述一些基本概念;然后介绍迄今为止最有希望的功率MOS结构,即V·MOS和VD·MOS晶体管中所使用的方法。 接着,我们叙述这些器件的电学性能,即阈值电压、电压—电流特性、欧姆(电阻)特性、饱和及准饱和范围,一次和二次击穿、安全工作区。还讨论了某些动态特性。最后,分析了功率MOS场效应晶体管的基本限制之一,即导通电阻与电压控制能力间的权衡;并提供了某些与其它功率器件的比较数据。     

高频控制开关用沟槽MOSFET的研究

高频控制开关用功率器件要同时具备极低的导通电阻和栅漏电荷值,从而降低导通损耗和开关损耗.基于器件与工艺模拟软件TsupremⅣ和Medici,研究了工艺参数和设计参数对沟槽MOSFET器件击穿电压、比导通电阻和栅漏电荷的影响,优化设计了耐压30 V的开关用沟槽MOSFET器件.对栅极充电曲线中平台段变倾斜的现象,运用沟道长度调制效应给出了解释.     

500V高压集成电路LCH1016的研制

本文采用N阱硅栅CMOS工艺和自绝缘偏移栅高压MOS器件结构，研制出500V高压集成电路LCH1016，重点讨论了高压器件结构对击穿电压的影响及其导通电阻特性，给出了LCH1016的电路逻辑、版图设计及工艺参数控制。     

CoolMOS导通电阻分析及与VDMOS的比较

为了克服传统功率MOS导通电阻与击穿电压之间的矛盾,提出了一种新的理想器件结构,称为超级结器件或CoolMOS,CoolMOS由一系列的P型和N型半导体薄层交替排列组成.在截止态时,由于p型和n型层中的耗尽区电场产生相互补偿效应,使p型和n型层的掺杂浓度可以做的很高而不会引起器件击穿电压的下降.导通时,这种高浓度的掺杂使器件的导通电阻明显降低.由于CoolMOS的这种独特器件结构,使它的电性能优于传统功率MOS.本文对CoolMOS导通电阻与击穿电压关系的理论计算表明,对CoolMOS横向器件:Ron·A=C·V2B,对纵向器件:Ron·A=C·VB,与纵向DMOS导通电阻与击穿电压之间Ron·A=C·V2.5B的关系相比,CoolMOS的导通电阻降低了约两个数量级.     

光MOS继电器的交流特性

一、光MOS继电器的特点光MOS继电器的内部结构如图1所示。由图可知光MOS继电器的内部结构与一般的光耦合器件非常相似。其外部开关与封装也与一般的光耦合器件一模一样(照片1)。由发光二极管发射的光经太阳能电池转换成电压,构成MOS场效应管的栅极偏置电压,控制MOS场效应管的通断。输出端用两个MOS场效应管串联连接,可以控制交流信号的通断。与机械触点式继电器相比,光MOS继电器具有     

功率MOS场效应晶体管达到超大规模集成密度

据仙童公司设在加州圣拉斐尔城的分立器件事业部的功率器件设计经理卡尔、A、萨沙曼说,仙童半导体公司的工程师借用三项超大规模集成加工技术制作出密度达280万单元/平方英寸的新一代功率MOS场效应晶体管电路。该集成密度大约是现行一代产品的三倍,比目前一些竞争公司正在研究的器件还要大一倍。仙童公司的第三代产品采用了投影光刻、等离子体腐蚀(用于接触窗口)、和快速热退火(形成极浅的结)等三项加工技术。据萨沙曼说,第三代功率MOS场效应管的导通电阻接近于理论极小值,即硅外延层的本征电导率可能采用通常工艺制作。“与目前的功率MOS FET技术相比,我们制作的器件的导通电阻更低,速度更高、芯片尺寸更小,而成本却更低。”     

新型电导率调制场效应管

美国无线电公司综合MOS功率晶体管、双极型晶体管和闸流管的优点研制成功一种新型MOS场效应功率管,命名为电导率调制场效应管(COMFET),其芯片面积为120平方毫米. 新器件的导通电阻比MOS场效应管小一个数量级;当20安漏极电流流过器件时,测得其电阻小于0.1欧.它的前向截止电压达400伏,反向为100伏,因此     

Extraction of the Inversion and Accumulation Layer Mobilities in n-Channel Trench DMOSFETs

A new method to extract both the inversion and accumulation layer mobilities of electrons in n-channel trench double-diffused MOSFETs (DMOSFETs) is proposed and implemented for the first time. First, a model is developed for the on-resistance of the n-channel trench DMOSFET. This on-resistance model is fitted to the experimental data measured from an experimental n-channel trench DMOSFET by the method of linear least squares fitting. A very good fit is obtained such that the average percentage error between the model curve and the experimental on-resistance is less than$pm$1%. The fitting parameters obtained are used to calculate the inversion and accumulation layer mobilities as a function of a wide range of effective electric field. The calculated mobilities agree with those previously reported for conventional MOSFETs. The results are useful for optimizing the performance and reliability of the trench DMOSFETs.     

Comparative study of drift region designs in RF LDMOSFETs

Systematic investigation of the drift region design of the RF LDMOSFET in terms of breakdown voltage, on-resistance, transconductance, capacitance and hot-carrier effects is presented. The incorporation of a source field plate allows for an increase of drift dose for a given breakdown voltage, which eases the tradeoff between the breakdown voltage and on-resistance, and the breakdown voltage and transconductance. However, the increased dose can significantly degrade hot-carrier reliability. A step-drift has enhanced hot-carrier immunity and lower capacitance, but, at the cost of increased on-state resistance and lower transconductance. Furthermore, a second origin of hot carriers is reported in the step-drift design, which may cause damage in the drift region. A deeper drift region design, which does not require an additional mask in comparison to the step-drift design, is investigated. The proposed approach shares all the advantages provided by the field plate design. Moreover, the lower concentration in the new drift region design leads to enhanced hot-carrier immunity.     

30 V UMOS中影响导通电阻平坦度的因素分析

功率MOSFET作为开关器件时,导通电阻的平坦度是衡量其性能的重要参数。研究影响导通电阻平坦度的因素,并对其进行优化,有助于改善器件的性能。低压UMOS中,沟道电阻是导通电阻的主要部分。文章以沟道电阻为分析对象,利用公式分析影响因素,通过Sentaurus TCAD仿真验证了导通电阻平坦度的变化趋势。通过改变P型基区离子注入剂量和栅氧层厚度进行仿真。仿真结果表明,通过减小栅氧层厚度和减少P型基区注入剂量,可获得较好的导通电阻平坦度。     

A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing

A novel technique for fabricating high reliability trench DMOSFETs using three mask layers is realized to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. This technique provides a unit cell with 2.3/spl sim/2.4 /spl mu/m pitch and a channel density of 100 Mcell/in/sup 2/. Specific on-resistance is 0.36 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 43 V at a gate voltage of 10 V and 5 A source-to-drain current. The time to breakdown of gate oxide grown on the hydrogen annealed trench surface is much longer than that of oxide grown on a nonhydrogen annealed trench surface.     

On-resistance of V-v.m.o.s. power transistors

An expression for the on-resistance of a V-groove vertical-channel m.o.s. (V-v.m.o.s.) transistor is presented. The expression relates the on-resistance to the geometry and resistivity of the drain drift region and is useful in optimising the drift region parameters for minimum on-resistance and maximum drain-source breakdown.     

低温下功率MOSFET的特性分析

文章完成了对功率MOSFET（Metal Oxide Semiconductor Field Effect Transistor）闽值电压和通态阻抗在77K-300K范围内的实验测试，并结合上述两个参数宽温区的数学模型进行了相应的分析．从实验结果中．我们发现阀值电压随温度的降低略有升高；而通态阻抗随温度的降低则下降得非常明显。通态阻抗是影响功率MOSFET开关损耗的重要参数，所以在低温下功率MOSFET的开关损耗将大幅度下降。     

A circuit for reducing on-resistance of a p-n-p-n device at low currents

This letter proposes a useful circuit which can reduce the on-resistance of a p-n-p-n device. This circuit is contrived from experimental results showing that the on-resistance decreases as the value of a resistor inserted between the gate and cathode terminals decreases. The basic operation and features of this circuit are discussed and its usefulness is verified experimentally. The p-n-p-n device having the circuit described here shows significant reduction in the on-resistance at the low forward-current region without degradation of characteristics such as gate triggering. This p-n-p-n device is useful for subscriber line interface circuits which need low on-resistance especially at low current levels.     

Self-aligned UMOSFET's with a specific on-resistance of 1 mΩ.cm2

This paper describes an improved UMOSFET with an ultralow specific on-resistance. This device utilizes a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 6 µm. This allows for a remarkable increase of channel density and, therefore, reduces the on-resistance per unit area significantly. Experimental devices have been fabricated, and a specific on-resistance of 1.0 mΩ . cm²with a breakdown voltage of 30 V has been achieved. This specific on-resistance is the lowest value ever reported for FET's.     

具有L型栅极场板的双槽双栅绝缘体上硅器件新结构

为了降低绝缘体上硅（SOI）功率器件的比导通电阻,同时提高击穿电压,利用场板（FP）技术,提出了一种具有L型栅极场板的双槽双栅SOI器件新结构.在双槽结构的基础上,在氧化槽中形成第二栅极,并延伸形成L型栅极场板.漂移区引入的氧化槽折叠了漂移区长度,提高了击穿电压;对称的双栅结构形成双导电沟道,加宽了电流纵向传输面积,使比导通电阻显著降低;L型场板对漂移区电场进行重塑,使漂移区浓度大幅度增加,比导通电阻进一步降低.仿真结果表明：在保证最高优值条件下,相比传统SOI结构,器件尺寸相同时,新结构的击穿电压提高了123%,比导通电阻降低了32%;击穿电压相同时,新结构的比导通电阻降低了87.5%;相比双槽SOI结构,器件尺寸相同时,新结构不仅保持了双槽结构的高压特性,而且比导通电阻降低了46%.     

低压VDMOSFET元胞尺寸设计

VDMOSFET的一个重要设计目标就是要在单位面积得到最小的导通电阻。理论分析了多晶硅栅长度LP和窗口扩散区长度LW对VDMOSFET特征电阻的影响,并通过大量计算得到了最小特征电阻时窗口扩散区长度LW的取值方法和多晶硅栅长度LP的取值范围。