一种新型ESD电压发生器的设计与调试

针对静电放电(Electro-static Discharge.简称ESD)对芯片造成损伤的现象,研究了静电放电发生的过程及产生的原因.首先阐述了几种常见的模拟静电放电过程的模型,然后利用彩色电视机的一体式行回扫变压器作为直流高压源、串联SCR作为高压开关,设计并制作出符合IEEE Std C62,38-1994标准的ESD人体模型实验发生仪器,并对ESD人体放电模型中的body/finger模型进行了实验模拟.最后给出放电电压为4kV时测量的ESD电流脉冲波形,并与理想放电波形进行对比,其结果验证了该方案的可行性和易操作性.     

集成电路静电放电模拟器校准与测量不确定度

集成电路静电放电模拟器是微电子元器件可靠性筛选的重要设备,通过模拟静电放电对器件的抗静电能力进行筛选.本文在分析静电放电模拟器工作原理的基础上,利用高频电流探头和高速率采样示波器实现了对模拟器的校准.文章还并结合校准实例,对测量不确定度进行了评定.     

电力行业标准《局部放电测量仪校准规范》解读(上)

针对电力行业标准<局部放电测量仪校准规范>即将颁布,该规范的主要起草人就其编写过程中遇到的技术难题及解决方法进行分析阐述,以其校准人员对该规范的相关内容有正确的理解.     

电力行业标准《局部放电测量仪校准规范》解读(下)

针对电力行业标准<局部放电测量仪校准规范>即将颁布,该规范的主要起草人就其编写过程中遇到的技术难题及解决方法进行分析阐述,以期校准人员对该规范的相关内容有正确的理解.     

空气式静电放电的实验分析

针对国际电工委员会标准IEC 61000-4-2静电放电抗扰度试验方法存在的问题,对空气式静电放电进行实验研究.利用新型静电放电(ESD)模拟测试系统,在较宽范围的电压电平下,用数字存储示波器对放电电流的上升时间、峰值、自制金属半圆环天线上的耦合电压峰一峰值进行测量.测量结果的分析表明:不同空气湿度下的ESD特性存在着...     

考虑寄生参数影响的芯片RC-HBM静电测试模型

采用常规的人体模型(Human Body Model,HBM)进行静电释放(Electro-Static Discharge,ESD)测试时往往容易受到寄生参数的影响,使得电源芯片抗静电能力测量值与实际抗静电能力存在偏差,导致劣质产品通过HBM ESD测试,影响电源芯片产品良品率的提升。为此,提出了一种RC-HBM模型,通过引入RC并联支路,校正因寄生参数引起的静电放电电流的偏差,满足电源芯片静电可靠性测试的要求。首先阐述了静电对电源芯片的损坏机理。其次,分析了寄生参数对ESD电流的影响,阐述了常规HBM ESD测试的局限性。并提出了一种新型的RC-HBM模型,给出了RC并联支路参数的设计依据。最后,通过批量实验验证了所提RC-HBM模型的准确性和合理性。     

ESD相关电场测量研究

对静电放电(ESD)过程的相关电场进行了理论计算和定性分析，然后利用两个不同测量方案对ESD电场进行了测量，对过渡区的测量波形和理论计算波形定性比较分析发现，二基本吻合。     

局部放电UHF检测仪校准方法研究

针对GIS开展的UHF法局部放电检测是目前主流的带电检测方法之一,现阶段局部放电UHF检测仪偏重于对局部放电的定性判断,迫切需要建立量值溯源链并评价检测结果的可信度。本文参考IEEE推荐的电场强度校准方法,对局部放电UHF检测仪关键参量的量值溯源方法和平台进行了研究。对电气设备内部的电场信号采样,根据示值与场强的对应关系换算出被试品测得的电场强度。通过校准平台,将被试品与标准电场强度进行比对,得出被试品的测量误差为-3.74 d B~+2.98 d B。试验表明基于传递标准和稳态电场校准局部放电UHF检测仪主要参量的方法是可行的。     

XLPE电缆内置传感器检测局部放电的带电校准技术研究

电力电缆出厂试验以及现场离线试验进行局部放电测试时,均采用以皮库(pC)表征的视在放电量来评价其绝缘水平。文中采用内置电容耦合方法进行XLPE电缆局部放电的带电检测,为了使检测结果与出厂试验等离线试验结果能够进行对比,将检测结果以视在放电电荷量形式呈现,需要提出该方法的校准方法。论文采用内置电容耦合法对基于等效电容作为分度电容的带电校准、基于频率响应的带电校准以及基于电缆等效电路仿真的带电校准等3种在线校准方法进行研究,并在实验室35 kV电缆上与IEC 60270:2000标准中规定的端部校准方法进行对比分析。实验结果显示,由于考虑了传感器与电缆金属护套间的杂散电容Cs,基于电缆等效电路仿真的内置电容耦合传感器的带电校准方法获得的校准系数准确度更高与标准端部校准有较好的吻合度。     

固定间隙的空气式静电放电

为更好地研究空气式静电放电,利用新型ESD模拟测试系统研究了固定间隙的空气式静电放电特性。在较宽范围的电压电平下,用数字存储示波器测量放电电流的上升时间、峰值、自制金属半圆环上的耦合电压峰-峰值,并记录了放电电流和耦合电压的波形。分析测量结果及其与放电电压和放电间隙之间的变化关系,可知在一定的间隙间距上,放电电流随着放电电压的增大而增大,高压放电也能产生上升沿比较陡的电流脉冲;在一定的放电电压下,存在着一个放电间隙间距使得放电电流峰值最大或耦合电压最大;不同电压下的频谱分布和能量分布不一样。     

聚合物ESD抑制器抑制特性的测试方法

为了消除静电放电时产生的辐射场对静电放电抑制器测试结果的影响,基于法拉第笼的屏蔽效应、依据国际电工委员会IEC61000-4-2标准和国军标GJB911-1990,利用静电放电模拟器和静电放电电流波形测试装置等设备,测试了某型号聚合物静电放电抑制器的抑制特性。测试结果表明,采用IEC61000-4-2标准规定的电流靶结合法拉第笼的方法,测试静电放电时通过抑制器的电流,能够保证电流波形不失真;而加在抑制器两端的电压,须使用有效带宽足够宽的电压探头配合示波器来测量,同时应尽可能消除静电放电时产生的辐射场对电压探头的影响。     

相参雷达信号源检定系统设计

提出了一种相参雷达信号源检定系统设计方案.该系统采用正交解调、A/D采样技术以及用DSP、FPGA等数字信号处理芯片对信号进行相关处理,能够完成对相参信号源的检定,并且介绍了系统总体框图及各个模块设计.     

A Case Study of Problems in JEDEC HBM ESD Test Standard

There is a current need for modification of EIA/JEDEC Human-Body model (HBM) electrostatic discharge (ESD) test standard, which does not define start and step test voltages. In the current standard, some measurements start at several kilovolts, which ignore the fact that ESD protection devices may fail under low voltage stresses. In this paper, a grounded-gate structure with an n-well ballast resistor connecting its drain and PAD is investigated for HBM ESD sustaining levels. When tested with a Zapmaster starting from 1 kV, the withstand voltage exceeds 8 kV, whereas the structure failed at 350 V when the test starts from 50 V. The test results from a transmission-line-pulsing system validate the phenomenon. The reason for the failure is also studied and confirmed with optical-beam-induced resistor change system failure analysis results. To address this general issue, a suggestion for improving the present HBM ESD testing standards for industry applications is made.      

Human-Body-Model Electrostatic-Discharge and Electrical-Overstress Studies of Buried-Heterostructure Semiconductor Lasers

Optoelectronic components such as laser diodes, light-emitting diodes, and photodiodes are susceptible to electrostatic discharge (ESD) and electrical overstress (EOS). Human-body model (HBM) is the most widely adopted method for the characterization of the ESD performance. In this paper, we report a comprehensive study of the ESD and EOS characteristics of buried-heterostructure (BH) semiconductor lasers using the HBM. Threshold current, optical power, optical spectrum, and reverse-bias current are characterized during the ESD study. We show that the ESD-failure thresholds depend upon the polarity. The chip can sustain the highest ESD stress under forward bias and the lowest one under forward/reverse bias. We also show that the BH lasers exhibit two types of ESD-degradation behavior. The soft degradation is characterized by a gradual increase in the threshold current, whereas the hard degradation is identified by a sudden jump in the threshold current during the ESD voltage ramp. The ESD-degradation behavior seems to be influenced by the cavity length. The failure-analysis results show that about 27% of the ESD failure is related to facet damage. The damage regions occur at the upper laser mesa structure and form preferentially on the bond-pad side. The preferential formation of the facet damage is suggestive of current-crowding effect. We have also found that the ESD-degradation behavior is a function of the facet damage. The soft-degradation failure shows a stronger correlation with the facet damage than the hard-degradation one. Finally, we demonstrate that the ESD performance of the laser can be improved by adding a protection diode.     

Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses

Several complex electrostatic discharge (ESD) failure mechanisms have been found in the interface circuits of an IC product with multiple separated power domains. In this case, the machine-model (MM) ESD robustness cannot achieve 150 V in this IC product with separated power domains, although it can pass the 2-kV human-body-model (HBM) ESD test. The negative-to-VDD (ND) mode MM ESD currents were discharged by circuitous current paths through interface circuits to cause the gate oxide damage, the junction filament, and the contact destruction of the internal transistors. The detailed discharging paths of ND-mode ESD failures were analyzed in this paper. In addition, some ESD protection designs have been illustrated and reviewed to further comprehend the protection strategies for cross-power-domain ESD events. Moreover, one new active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13- $muhbox{m}$ CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively.      

900 MHZ radio‐frequency identification rectifier with optimization and reusing of electro‐static discharges protections in 180 nm digital CMOS technology

Sensitivity and electro‐static discharges (ESD) protection level are crucial parameters for any Ultra High‐Frequency (UHF) power rectifier–harvester designed for radio‐frequency identification (RFID) devices. While sensitivity limits the reading range of the interrogator‐to‐tag communication link, the requirement for an adequate protection against ESD is enforced in commercial devices connected to a printed antenna. Both resistive and capacitive parasitics of the protection circuits severely affect RF performance of the device. In the paper, a rectifier for UHF RFID embedding an ESD protection for 2 kV human‐body discharge model (HBM) level is proposed. The target of a low added parasitic capacitance is achieved by adapting the protection circuit to the RFID rectifier and reusing the ESD clamp for additional functions being mandatory in a UHF RFID front end. The layout of the ESD clamp has been optimized for minimum parasitic resistance without sacrificing the protection level. Two UHF harvesters were implemented in a 180 nm digital complementary metal‐oxide semiconductor (CMOS) technology, featuring a minimum sensitivity of ?15.5 dBm with an ESD protection level of 2 kV HBM. Copyright © 2014 John Wiley & Sons, Ltd.     

相参雷达信号源检定技术研究

介绍了研制相参雷达信号源检定设备的紧迫性和研究现状,分析了相参脉冲串信号、线性调频信号及多普勒频移特性,提出了相参性、线性调频特性、多普勒频移特性的检定理论方法,初步给出了检定的总体思路.将为研制相参雷达信号源检定系统提供借鉴,具有一定的工程应用价值.     

Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls

An abnormal failure mechanism due to ESD pulse applied on the nonconnected (NC) solder balls of a high-pin-count (683 balls) BGA packaged chipset IC is presented. The ESD test results of the IC product were found below human-body-model (HBM) 2 kV when stressing all balls or only stressing NC balls, but above HBM 3 kV when stressing all balls excluding NC balls. Failure analyses, including scanning electron microscopy (SEM) photographs and the measurement of current waveforms during ESD discharging event, have been performed. With a new proposed equivalent model, a clear explanation on this unusual phenomenon is found to have a high correlation to the small capacitor method (SCM). Several solutions to overcome this failure mechanism are also discussed.     

ESD电流的解析表达式与数值解

分析IEC6100042静电放电(ESD)电流波形典型拟合解析表达式表明,这种由有限点拟合曲线的纯数学方式存在拟合的多样性,无可依据的物理基础。因而根据ESD物理特性提出了一种通过数值计算等效电路模型获得ESD电流数值解的方法,由该方法算出的电流峰值、上升时间、i30ns、i60ns等关键参数与IEC610042电流波形参数的相对误差的最大值均<1.6‰,为ESD辐射电磁场研究提供了有效的手段。