Effects of ionizing radiation on oxidized silicon surfaces and planar devices

This paper examines in detail the effects of high and low energy electron, X-ray, and ultraviolet radiation on oxidized silicon surfaces and planar devices. Two permanent effects of ionizing radiation on oxidized silicon surfaces are distinguished: 1) The buildup of a positive space charge within the oxide, and 2) The creation of fast surface states at the oxide-silicon interface resulting in increased surface recombination velocity. The dependence of these effects on dose and dose rate, on bias applied during irradiation, and on structural parameters is discussed and a theory is presented which accounts for the observed features of the space-charge buildup. This theory involves trapping of holes which are generated within the oxide by the radiation. It is shown that all details of the experimental observations can be accounted for by assuming a high density of hole traps near the oxide-silicon interface which decays rapidly with distance into the oxide. Radiation-induced changes in the characteristics of MOS and junction field-effect transistors, p-n junction diodes, and p-n-p and n-p-n transistors are reported and examined in terms of the above two effects. It is shown that the charge buildup causes shifts in the operating point of MOS transistors, catastrophic increases in the reverse current of p-n junctions, and variations in their breakdown voltage. The increase in fast surface-state density is responsible for the lowering of the transconductance of MOS transistors and, in combination with the space-charge buildup, for the degradation of the current gain in bipolar transistors. It is shown that junction field-effect transistors are relatively insensitive to both effects of ionizing radiation and therefore offer the most promise for use in ionizing radiation environments.     

High-voltage, large-area planar devices

By using basic elements of planar technology, a process and design for manufacturing 2-inch diameter rectifiers with up to 8.0 kV blocking voltage capability is presented. The diode structure used has a field plate overlay, a metallic equipotential ring (EQR), and a layer of resistive polycrystalline silicon film over the oxide and between the field plate and EQR electrodes. The results of this work offer new methods for fabricating power devices with higher blocking voltages than the traditional etched mesa devices.     

Design, tolerance analysis, and fabrication of silicon oxynitridebased planar optical waveguides for communication devices

Planar optical waveguiding structures for application in communication networks are highly demanding with respect to low insertion loss, efficient fiber-to-chip coupling, polarization independent operation, high integration density, reliable fabrication, and last but not least cost efficiency. When applying silicon oxynitride, which is a very versatile material, planar waveguiding structures can be designed having the potential of meeting all those requirements. In this paper, we will describe the design of such a waveguiding structure, demonstrate the practical feasibility of realizing this structure and discuss the preliminary measurement results     

Delay structures with planar Gunn devices

A pulse delay obtained with the aid of the domain travelling effect in Gunn devices is described. For this purpose, the planar Gunn devices contain, in addition to a trigger electrode, a capacitive electrode for coupling out the signal. Experimental results are given for the single component and a monolithic integrated cascade circuit. The devices are appropriate for constructing dynamic shift registers in the sub-nanosecond range.     

CW Performances of planar Gunn-effect devices

CW operation of planar Gunn-effect devices was experimentally investigated. The subthreshold potential profile along the active layer was found to redistribute with a time constant of a few hundred microseconds at room temperature, resulting in a high-field layer near the anode. The trigger sensitivity of Schottky-gate devices was also found to be dependent on the trigger rate for frequencies higher than 1 MHz. Electron-trapping effects were confirmed to play an important role in this phenomenon. The device with a "gate notch" in which the active layer thickness is reduced under the gate electrode, was ascertained to be effective in suppressing such anomalous behavior. By performing improvements on the device structure and the circuit construction, the integrated 2-bit shift register was developed. The fabricated circuit was successfully operated at a clock rate of 2.7 GHz under dc bias. Ring-counter operation was also observed by utilizing the present circuit.     

Scaling silicon MOSFET's for 77 K operation

Using the gradual channel approximation and the velocity-field relationship appropriate to holes in silicon, the static characteristics of Si MOSFETs at 77 K are scaled from those at 300 K to provide similar static characteristics at the two temperatures. Compared to 300 K, the approximate scaling factors for 77 K are 1/4 for voltage, 1/3 for current, 1/12 for static power, 1/16 for dynamic power, and 1/20 for the delay-power product. At 77 K the transconductance is increased by 20% compared to room temperature. Agreement between theory and experiment on p-channel devices is good for channel lengths greater than about 5 μm but the agreement decreases with decreasing channel length. Because the drain voltage required for current saturation decreases with decreasing temperature, circuit operation at supply voltages below 1 V appears feasible     

Scaling limits in batch-fabricated silicon pressure sensors

The scaling properties of silicon capacitive and piezoresistive pressure sensors are described. An evaluation of the various noise mechanisms and pressure offsets in the scaled devices is presented, including Brownian noise, electrical noise, electrostatic pressure variations and pressure offset due to resistor mismatch. The analysis of diaphragm deflection includes the effects of intrinsic stress and the transition from plate theory to membrane theory. Both ultraminiature and ultrasensitive sensors are considered. Ultraminiature piezoresistive sensors with diaphragms measuring 100 µm in length and resolving 1 mmHg should be possible using present technology as well as ultrasensitive capacitive sensors that resolve 1 µmHg.     

Scaling limitations of silicon multichannel recording probes

This paper describes the scaling limitations of multichannel recording probes fabricated for use in neurophysiology using silicon integrated circuit technologies. Scaled silicon probe substrates 8 microns thick and 16 microns wide can be fabricated using boron etch-stop techniques. Theoretical expressions for calculating the thickness and width of silicon substrates have been derived and agree closely with experimental results. The effects of scaling probe dimensions on its strength and stiffness are described. The probe shank dimensions can be designed to vary the strength and stiffness for different applications. The scaled silicon substrates have a fracture stress of about 2 x 10(10) dyn/cm2, which is about six times that of bulk silicon, and are strong and very flexible. Scaling the feature sizes of recording electrode arrays down to 1 micron is possible with less than 1 percent electrical crosstalk between channels.     

Flicker noise in silicon planar transistors

Flicker noise may be characterised by a single parameter ?F, which is the frequency at which flicker noise becomes equal to shot noise. Many devices show ?F to be as low as 60 Hz, and give a noise figure of <1dB at 25 Hz. This is not in accordance with a recently published formula.     

Low-operating-voltage integrated silicon light-emitting devices

A solution is presented for the fabrication of low-voltage, low-power (<4.25 V and <5 mW) silicon light-emitting devices (Si-LEDs), utilizing standard very large scale integration technology without any adaptation. Accordingly, they can be integrated with their signal processing CMOS and BiCMOS circuits on the same chip. This enables the fabrication of much needed all-silicon monolithic optoelectronic systems operated by a single supply. The structural details of two distinctly different line-patterned Si-LEDs are presented, composed of heavily doped n/sup +/p/sup +/ junctions, made by BiCMOS n/sup +/ sinker and PMOS p/sup +/ source/drain doped regions, respectively. Using this approach, other Si-LED structures can be designed to yield low- or high-voltage Si-LED operation as well. Light is emitted at low reverse bias as a result of quantum transitions of carriers, generated by field emission, as indicated by the low reverse breakdown voltage V/sub B/, the soft "knee" I-V characteristics and the negative temperature coefficient of V/sub B/. The optical performance data show that, at low reverse operating current I/sub R/, the overall emitted light intensity L is a nonlinear function of I/sub R/ and becomes linear at higher I/sub R/. A bell-shaped light spectrum is obtained, with an enhanced short wavelength and attenuated long-wavelength radiation, relative to that of avalanche Si-LEDs.     

Voids in silicon power devices

Formation and properties of voids in silicon obtained by high dose helium implants are described and discussed in view of their applications in localised lifetime engineering. Voids are stable even after huge thermal budget as observed by transmission electron microscopy analyses. Leakage measurements on p⁺n diodes as a function of temperature allowed us to determine the hole trap level (ΔE=0.16 from the Fermi level above the valence band) and the generation and recombination lifetime values. To demonstrate the advantage of the method in power device applications, high-speed IGBTs were fabricated both with voids in the buffer layer or with unlocalised recombination centres. The devices with voids show a lower on-resistance and a fast turn-off behaviour. Map measurements on 150 mm silicon wafers demonstrate the good uniformity that can be reached by the method in an industrial environment.     

Extremely scaled silicon nano-CMOS devices

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.     

Bonded planar structures for efficient surface-wave devices

Acoustic surface waves have been transferred from yz lithium niobate to s.t. cut quartz surfaces across thin epoxy-resin bonds in a planar geometry. In the best case to date, only 7 dB transmission loss was measured through two bonds at 50 MHz in a lithium-niobate-quartz-lithium-niobate structure.     

MCVD planar substrates for UV-written waveguide devices

A method for fabricating planar silica substrates via modified chemical vapour deposition (MCVD) and a modified fibre drawing technique is presented. Long lengths of planar material are generated from a single substrate offering a potentially low-cost alternative to existing planar substrate deposition processes. Buried straight and splitting waveguide channels, as well as Bragg gratings, are inscribed in the planar material using direct UV-writing technology, and the results are reported     

Recent developments in silicon optoelectronic devices

Due to the rapid growth of the internet and multi-media communication networks, there are urgent needs and tremendous commercial values in the development of optoelectronics integrated circuits (OEICs). This work reviews the recent developments and the prospect of silicon-based integrated optoelectronic circuits (Si-OEICs). The technological aspects of porous silicon and oxynitride devices for integrated optoelectronic applications are discussed. Some optoelectronic devices being realized with these technologies are described. Recent achievements indicate that the present constraints for using Si-based materials in optoelectronics are mainly technological rather than physical. Once these technological difficulties are resolved, the realization and applications of Si-OEICs will grow rapidly.     

ESD保护器件在多晶硅上的实现

静电放电现象是导致集成电路损坏的一个重要原因,目前绝大多数集成电路中的ESD保护电路都是在硅片上实现的,这将占用一定的硅片面积,提升电路的成本.如果能够在多晶硅层(垂直空间)实现ESD保护器件,就能够节约一定的面积,从而节约成本.介绍了对于在多晶硅上实现的静电保护器件的研究结果.     

Crystalline oxide-based devices on silicon substrates

We have developed a process to grow epitaxial SrTiO₃ (STO) on Si. This STO/Si substrate can then be used as a pseudo substrate for the further deposition of many other oxides that are closely lattice matched to STO. The STO is grown by molecular-beam epitaxy (MBE) with a subsequent oxide layer deposited either by MBE or sol-gel deposition. The pseudo substrate has been used to demonstrate ferroelectric devices and piezoelectric devices. Ferroelectric capacitors using epitaxial BaTiO₃ (BTO) show a memory window of 0.5 V; however, the retention time for these devices is short because of the depolarization field caused by the silicon-oxide interface layer used to improve the band alignment of the BTO/Si interface. Surface acoustic wave (SAW) resonators using epitaxial Pb(Zr,Ti)O₃ show excellent response with a coupling coefficient of 4.6% and a velocity of 2,844 m/s.     

Junction parameters for silicon devices characterization

An innovative method for device characterization is developed to qualify microelectronic devices. The method is based on parameter extraction from the junction I–V characteristics. Their evolution during electrical aging and ionizing radiation experiments allows an evaluation of the magnitude of the degradation. Results obtained with commercial samples show a signature of both manufacturer and technological processes. This method is easy to implement in a control process for device characterization.