共查询到19条相似文献,搜索用时 171 毫秒
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基于双CPU共享RAM技术,从经济实用的角度出发,提出了一种利用单端口存储器构建双端口共享存储器的方法。根据62256单端口存储器的工作原理和结构设计特点,利用单向缓冲器芯片74ALS244对存储器的地址总线、控制总线进行扩展,利用双向缓冲器芯片74ALS245对存储器的数据总线进行扩展,存储器的地址线、数据线和控制线分别由单路变为双路,再通过选通信号实现对各路总线的读写控制。经扩展的单端口存储器可实现双端口存储器的全部功能,具有成本低、容量大、性能稳定的优点,可广泛应用于硬件设计。 相似文献
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《现代电子技术》2016,(16):83-87
针对多核处理器的特点提出一种新型的异构多核DSP处理器结构。主处理器为通用处理器,作为控制密集型处理器核用于系统管理和控制;8个DSP作为计算密集型处理器核,用于大信息量融合计算。详细设计8个DSP之间的No C互连结构。首先采用2×4 2D Turos结构进行单个路由节点结构的设计,包括数据包格式、路由和仲裁设计;其次对路由节点进行编码、路由算法设计和确定节点路由方向。该结构具有总线局部通信带宽高的优点,采用No C的易扩展性和No C在各DSP之间通信的并行性使系统规模易于扩展并满足大批量数据传输要求。最后通过仿真实验,验证了该设计的有效性,为后续多核处理器的设计与实现打下坚实的技术基础。 相似文献
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本文提出了基于FPGA嵌入式系统控制开关磁阻电机(SRM)的控制方法,以微处理器软核MicroBlaze作为主控制器,以Xilinx公司提供的通用IP核设计出系统外围设备,用Verilog HDL硬件语言设计出专用的逻辑控制模块,经过CoreConnect片上总线通信链,实现了在一块FPGA芯片上完成了SRM的控制算法策略和外围接口逻辑电路,大大增加的系统的可靠性和性价比。最后以Xilinx公司SPARTAN3E系列的FPGA进行了设计,验证了设计的正确性和可行性。 相似文献
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基于Tsi148的PCI—VME总线接口设计 总被引:1,自引:0,他引:1
VME总线是一种开放式工业计算机总线,在VME总线多主处理计算机系统中,通常需要进行PCI总线与VME总线接口互连。这里分析了业界最先进的PCI—VME总线互连芯片Tsil48的原理与功能,介绍Tsi148在VME总线智能模块中进行PCI—VME接口互连的方法,给出通过本地PCI总线接口进行Tsi148初始化和VME系统配置的软件流程。实践表明,采用Tsi148进行PCI—VME互连设计,实现了VME总线的高速数据传输和控制功能,并在实际应用中取得了良好的效果。 相似文献
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Jian Liang Laffely A. Srinivasan S. Tessier R. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(7):711-726
A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth signal processing applications including an MPEG-2 video encoder and a Doppler radar processor have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based system-on-chip (SoC) approach by up to a factor of five. A VLSI implementation of the communication architecture indicates clock rates of 400 MHz in 0.18-/spl mu/m technology for sustained on-chip communication. In comparison to previously-published results for an MPEG-2 decoder, our on-chip interconnect shows a runtime improvement of over a factor of four. 相似文献
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Mandal C. Chakrabarti P.P. Ghose S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2000,8(6):747-750
We present here a technique for allocation and binding for data path synthesis (DPS) using a Genetic Algorithm (GA) approach. This GA uses an unconventional crossover mechanism relying on a force directed data path binding completion algorithm. The data path is synthesized using some supplied design parameters. A bus-based interconnection scheme, use of multi-port memories, and provision for multicycling and pipelining are the main features of this system. The method presented here has been applied to standard benchmark examples and the results obtained are promising 相似文献
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非直角互连——布线技术发展的新趋势 总被引:4,自引:1,他引:3
由于集成电路制造工艺的不断提高 ,集成电路的设计规模遵循Moore定律持续向前发展 ,并出现了系统级芯片 (SOC)这一新的集成电路设计概念 .同时遇到的困难之一是互连线成为影响电路性能的决定因素 :芯片速度变慢、功耗增大、噪声干扰加剧 .若采用以往基于直角互连结构的基础模型进行互连线性能的优化 ,其能力受到限制 .于是 ,人们试图采用其他互连结构作为突破途径 ,以实现高性能的集成电路 .在这种技术需求与目前工艺支持的背景下 ,从 2 0世纪 90年代初出现的关于非直角互连的零散的、试探性的研究 ,将成为国际上布线领域新的热点研究方向 . 相似文献
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Recently, the use of multiprocessor system-on-chip (MP-SoC) platforms has emerged as an important integrated circuit design trend for high-performance computing applications. As the number of reusable intellectual property (IP) blocks on such platforms continues to increase, many have argued that monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these leading-edge SoCs. While hierarchical system integration using multiple smaller buses connected through repeaters or bridges offer possible solutions, such approaches tend to be ad hoc in nature, and therefore, lack generality and scalability. Instead, many different forms of network on chip (NoC) architectures have been proposed in the past few years to specifically address this problem. We believe that the NoC approach will ultimately be the preferred communication fabric for next generation designs. To support this conjecture, this paper demonstrates, through detailed circuit design and timing analysis that different proposed NoC architectures to date are guaranteed to achieve the minimum possible clock cycle times in a given CMOS technology, usually specified in normalized units as 10-15 FO4 delays. This is contrasted with the bus-based approach, which may require several design iterations to deliver the same performance when the number of IP blocks connected to the bus exceeds certain limits. 相似文献
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随着芯片集成制造工艺的日益发展,拥有多级Cache的片上多处理器(CMP)已成为桌面应用和高端计算的主流平台.为了优化程序在CMP下运行性能,文中以Pin工具软件为基础,提出并设计了一个面向CMP体系架构的多级Cache访问模拟器——CCSim.该模拟器不仅可以模拟同构CMP下传统方式的Cache访问,而且还可以对CMP中最后一级共享Cache的竞争访问以及非传统方式的Barcelona式Cache访问模式进行模拟分析. 相似文献
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Banerjee K. Souri S.J. Kapur P. Saraswat K.C. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2001,89(5):602-633
Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined 相似文献
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As technology scales toward deep submicron, the integration of complete system-on-chip (SoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. Until recently, the design-space exploration for SoCs has been mainly focused on the computational aspects of the problem. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from computation-based to communication-based designs becomes mandatory. As a result, the communication architecture plays a major role in the area, performance and energy consumption of the overall systems [Pasricha S, Dutt N. On-chip communication architectures: system on chip interconnect. Amsterdam: Elsevier Inc.; 2008, Kim J, Verbauwhede I, Chang MCF. Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Trans VLSI Syst 2007;15(8):881-94].This article presents a structure of a wrapper as a component of Code Division Multiple Access, CDMA, based shared bus architecture in a SoC. Two types of wrappers can be identified, master and slave. A master wrapper is located between the arbiter and CDMA coded physical interconnect, while a slave connects the CDMA coded bus with memory/peripheral module. In the proposal, only bus lines that carry address and data signals are CDMA coded. We implemented a pair of master-slave wrapper described in VHDL and confirmed its functionality using testbenches. Also we synthesized wrappers using a Xilinx Spartan and Virtex devices to determine resource requirements in respect to a number of equivalent gates, communication bandwidth, latency and power consumption. Specifically we involved a Design_Quality, DQ, metric for wrapper performance evaluation. A pair of master-slave wrapper seems to occupy appropriate space, in average 2000 equivalent gates, considering CPU cost of about 30,000 gates, what is less than 8% of hardware overhead per CPU. We also present experimental results which show that benefits of involving CDMA coding relates both to decreasing a number of bus lines and accomplishing simultaneous multiple master-slave connections at relatively low-power consumption and high communication bandwidth. Convenient range indices RW and RR to determine data transfer rate for Write and Read operations in multiprocessor bus systems that use TDMA and CDMA data transfer techniques. The obtained results show that increased data transfer latencies involved by CDMA data transfer are compensated by simultaneous master-slave transfers. 相似文献
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分布式并行计算的发展对嵌入式系统互联技术提出了更高的要求,RapidIO可提供芯片间、板间的高性能互联,传输效率高于PCIE和千兆以太网。文中给出了一种基于RapidIO的双主机节点嵌入式系统互联的设计方案、硬件设计及其软件实现,并对系统功能和性能进行验证。验证结果表明,该系统性能稳定、可靠,并为新一代高性能嵌入式系统互联提供了良好的解决方案。 相似文献