Passive geosynchronous SAR system reusing backscattered digitalaudio broadcasting signals

A synthetic aperture radar (SAR) is considered, located on a geosynchronous receiver, and illuminated by the backscattered energy of satellite broadcast digital audio or television signals. The principal application of such a passive system could be differential interferometry, since even low spatial resolution coupled to zero baseline would be useful; however, other imaging applications could be envisaged and even some topographic capabilities if a baseline is created by ellipticizing the receiver's orbit. Spatial resolution, link budget, and possible focusing techniques are evaluated     

An improved π/4-QPSK with nonredundant error correction forsatellite mobile broadcasting

An improved π/4-quadrature phase-shift keying (QPSK) receiver that incorporates a simple nonredundant error correction (NEC) structure is proposed for satellite and land-mobile digital broadcasting. The bit-error rate (BER) performance of the π/4-QPSK with NEC is analyzed and evaluated in a fast Rician fading and additive white Gaussian noise. (AWGN) environment using computer simulation. It is demonstrated that with simple electronics the performance of a noncoherently detected π/4-QPSK signal in both AWGN and fast Rician fading can be improved. When the K-factor (a ratio of average power of multipath signal to direct path power) of the Rician channel decreases, the improvement increases. An improvement of 1.2 dB could be obtained at a BER of 10^-4 in the AWGN channel. This performance gain is achieved without requiring any signal redundancy and additional bandwidth. Three types of noncoherent detection schemes of π/4QPSK with NEC structure, such as intermediate frequency band differential detection, baseband differential detection, and FM discriminator, are discussed. It is concluded that the π/4-QPSK with NEC is an attractive scheme for power-limited satellite land-mobile broadcasting systems     

Efficient codes for single error detection and partial single error correction

Coding schemes are proposed for error control in systems where individual blocks of information are organised as two sub-blocks each requiring a different degree of error control. The codes described guarantee single error correction in one sub-block and provide single error detection and partial single error correction in the other. The main advantages are savings in redundancy and ability to use standard encoding/decoding procedures.     

Built-in testable error detection and correction

A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented that uses up to 65% less test hardware than customary BIT implementations. A 1-μm CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 μs at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verify the effectiveness of built-in test     

An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction

An integrated adaptive-output switching converter is presented. This converter adopts one-cycle control for fast line response and dual error correction loops for tight load regulation. A dc level shifting technique is proposed to eliminate the use of negative supply and reference voltages in the controller and make the design compatible with standard digital CMOS process. The design accommodates both continuous and discontinuous conduction operations. To further enhance the efficiency, dynamic loss control on the power transistors is proposed to minimize the sum of switching and conduction losses. The design can be extended to other dc-dc and ac-dc conversions. The prototype of the buck converter was fabricated with a standard 0.5-/spl mu/m digital CMOS process. Experimental results show that the converter is well regulated over an output range of 0.9-2.5 V, with a supply voltage of 3.3 V. The tracking speeds are 12.25 /spl mu/s/V for a 1.6-V step-up output change and 13.75 /spl mu/s/V for a 1.6-V step-down output change, respectively, which are much faster than existing counterparts. Maximum efficiency of 93.7% is achieved and high efficiency above 75% is retained over an output power ranging from 10 to 450 mW.     

Error correction and error detection techniques for wireless ATM systems

Error correction and error detection techniques are often used in wireless transmission systems. The Asynchronous Transfer Mode (ATM) employs Header Error Control (HEC). Since ATM specifications have been developed for high‐quality optical fiber transmission systems, HEC has single‐bit error correction and multiple‐bit error detection capabilities. When HEC detects multiple‐bit error, the cell is discarded. However, wireless ATM requires a more powerful Forward Error Correction (FEC) scheme to improve the Bit Error Rate (BER) performance resulting in a reduction in the transmission power and antenna size. This concatenation of wireless FEC and HEC of the ATM may effect cell loss performance. This paper proposes error correction and error detection techniques suitable for wireless ATM and analyzes the performance of the proposed schemes. This revised version was published online in June 2006 with corrections to the Cover Date.     

Using codes for error correction and detection (Corresp.)

A linear codeCover GF(q)is good fort-error-correction and error detection ifP(C,t;epsilon) leq P(C,t;(q - 1)/q)for allepsilon, 0 leq epsilon leq (q - 1)/q, whereP(C, t; epsilon)is the probability of an undetected error after a codeword inCis transmitted over aq-ary symmetric channel with error probabilityepsilonand correction is performed for all error patterns withtor fewer errors. A sufficient condition for a code to be good is derived. This sufficient condition is easy to check, and examples to illustrate the method are given.     

基于数据驱动的不规则用电检测误差校正系统设计

为准确获取电网用户的用电消耗数据,实现对电网环境的实时监测,设计基于数据驱动的不规则用电检测误差校正系统.借助用电检测电路,调度步进式校正电机与EMI滤波器间的即时连接关系,实现系统的硬件执行环境搭建.在此基础上,过滤已生成的电网用户电量消耗数据,通过求取不规则电负荷特征的方式,设置必要的误差校正维度条件,实现系统的软...     

改进的S模式纠错算法

对检测到错误的S模式应答信号报文纠错,传统的方法是查表法,不仅效率很低,而且要求很大的存储空间存放错误图样,不适合工程应用。通过对S模式应答信号的干扰情况、编译码方式及循环码特性的深入研究,提出了余数计算的改进方法;再结合使用码元置信度,实现了能快速、准确定位误码并纠正它们的算法。改进的纠错算法不仅效率高,而且占用系统资源少,易于硬件实现,其有效性已得到工程应用的验证。     

雷达系统误差的测量和修正方法

在分析雷达系统误差特性的基础上,根据工程经验,提出雷达系统误差的测量方法、计算方法、置信度分析和修正方法,并给出实例。     

A NOVEL CONCURRENT ERROR DETECTION/ CORRECTION SCHEME FOR FFT

By converting DFT of a data sequence into two partial transforms, a novel concurrent error detection/correction scheme for FFT networks is proposed based on coding theory. The scheme is realized in the computing procedure of FFT, which is different from the methods available, and has more error detection/correction capability than that of the known methods.     

一氧化碳检测与排放回收综合控制系统的设计

为了设计一种CO气体检测与排放回收综合控制系统,采用可调谐半导体激光吸收光谱技术,利用单片机MC9S12DG128B作为核心控制器产生激光调制信号,通过采集经气体吸收后的光功率和2次谐波信号来分析气体浓度,把气体浓度信息上传到工控机进行实时监控。结果表明,CO激光检测气体灵敏度高、选择性强、响应速度快、能连续分析和抗干扰性能好,满足工业现场的要求。     

Incremental digital position encoder with error detection and correction

A digital position encoder is described which combines features of absolute and incremental encoders. A track encoded with a pseudorandom sequence provides absolute position information for an incremental encoder, allowing the detection and correction of errors, while requiring only two code tracks and four read heads.<>     

A power-based unequal error protection system for digital cinema broadcasting over wireless channels

This paper deals with the efficient and robust wireless broadcasting of JPEG2000 digital cinema (DC) streams from studios to theatres. Several unequal error protection (UEP) techniques have been proposed in literature for the transmission of JPEG2000 images. Some are based on variable forward error correction (FEC) coding applied to different parts of the stream according to their importance. Alternatively, UEP can be achieved by means of unequal power allocation (UPA) schemes based on differentiated transmission power over the stream. On the other hand, in DC applications UPA achieves weak performance if considered as the only protection strategy, unless high-power budget is assigned to transmission. This work proposes a novel hybrid FEC–UPA system adopting the resilience tools of the JPEG2000 wireless (JPWL) standard. The JPWL stream is partitioned into a certain number of packet groups to which “light” FEC coding is applied. Groups are then transmitted through separate wavelet packet division multiplexing (WPDM) sub-channels at different power. Both stream partitioning and UPA are driven by the sensibilities of the JPWL packets to the channel errors. The novelty of the proposed technique relies on the use of JPWL error resilience tools for the codestream partitioning, on optimized UPA among JPWL packets based on genetic algorithms (GA) and supported by “light” FEC channel coding. The proposed system is compared to the state of the art UEP techniques on JPEG2000 transmission. The performance is evaluated in case of transmission over wireless channels with both sparse and packet error statistics. Experiments show that the proposed approach allows achieving an average peak signal-to-noise ratio (PSNR) on the reconstructed frames compliant to the standard quality required by DC applications (40 dB) for bit error rate (BER) up to 10⁻⁴.     

惯性/景象匹配组合导航系统的误差校正研究

惯性/景象匹配组合导航系统(INS/SMNS)的组合方式,实际上是一种不等间距、非实时性的有限点校正。为了提高景象匹配和惯导系统的组合精度,进一步达到子像素级的水平,完成景象匹配对惯导系统累积误差的校正,提出了多点连续校正的方法。分析了进行校正的具体前提条件,推导了不同数目匹配点时,对应的简化惯性导航系统输出误差校正方程。根据简化的误差方程和惯性导航系统的输出值,求解出位置误差和速度误差。比较了单点、两点、三点、四点以及五点校正的结果。仿真结果表明:当匹配点个数越多,求解出的位置误差、速度误差精度越高。从而得出景象匹配误差校正精度主要取决于两个因素即匹配点的个数和校正的实时性的结论。     

Undetected error probabilities of binary primitive BCH codes forboth error correction and detection

We investigate the undetected error probabilities for bounded-distance decoding of binary primitive BCH codes when they are used for both error correction and detection on a binary symmetric channel. We show that the undetected error probability of binary linear codes can be simplified and quantified if the weight distribution of the code is binomial-like. We obtain bounds on the undetected error probability of binary primitive BCH codes by applying the result to the code and show that the bounds are quantified by the deviation factor of the true weight distribution from the binomial-like weight distribution     

Poor error correction codes are poor error detection codes (Corresp.)

We show that binary group codes that do not satisfy the asymptotic Varshamov-Gilbert bound have an undesirable characteristic when used as error detection codes for transmission over the binary symmetric channel.     

Enhanced architectures for soft error detection and correction in combinational and sequential circuits

In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26–28% lower than the TMR.     

三维激光扫描系统的固有误差校正算法

分析了三维激光扫描系统固有误差的来源,结合数学模型及实验数据,提出了相应的校正算法,并在实验中得到验证。从概率统计学角度分析激光测距仪固有误差的统计特性,增大平均次数的同时,减小测距仪测距误差;使用最小二乘法从实验数据中获取电机的动态角度误差,对理论角度进行校正后,得到电机实际转动角度;针对双振镜系统的非线性扫描失真,动态改变扫描范围,减小枕形误差。使用Matlab分析误差校正算法,并搭建实验平台测试上述算法,实验结果表明,对系统的测距误差、角度误差、枕形误差校正后,三维激光扫描系统的精度有较大的提高。