一种高速低功耗10位逐次逼近模数转换器设计

通过分析并优化逐次逼近模数转换器(SAR ADC)的工作时序,设计并实现了一种高速、低功耗、具有误差补偿的10位100 MS/s A/D转换器。该芯片采用TSMC 0.13 μm CMOS工艺进行设计。后仿真结果表明,在1.2 V电源电压、20.3125 MHz输入信号频率、100 MHz采样频率下,模数转换器的无杂散动态范围(SFDR)为68.1 dB,有效位数(ENOB)达到9.41位,整体功耗为0.865 mW,FoM值为15 fJ/conv。芯片核心电路面积为(0.02×0.02) mm²。     

低功耗、全差分流水线操作CMOS A/D转换器

提出一种基于运算跨导放大器共享技术的流水线操作A/D转换器体系结构,其优点是可以大幅度降低芯片的功耗和面积.采用这种结构设计了一个10位20MS/s转换速率的全差分流水线操作A/D转换器,并用CSMC 0.6μm工艺实现.测试结果表明,积分非线性为1.95LSB,微分非线性为1.75LSB;在6MHz/s采样频率下,对1.84MHz信号转换的无杂散动态范围为55.8dB;在5V工作电压、20MHz/s采样频率下,功耗为65mW.     

一种低功耗12位30 MHz流水线A/D转换器

设计了一种12位30 MHz 1.8 V流水线结构A/D转换器,该A/D转换器采用相邻级运算放大器共享技术和逐级电容缩减技术,其优点是可以大大减小芯片的功耗和面积.电路采用级联一个高性能前置采样保持单元和五个运放共享的1.5位/级MDAC,并采用栅压自举开关和动态比较器来降低功耗.结果显示,该ADC能够工作在欠采样情况下,有效输入带宽达到50 MHz.在输入频率达到奈奎斯特频率范围内,整个ADC的有效位数始终高于10.4位.电路使用TSMC 0.18 μm 1P6M CMOS工艺,在30 MHz全速采样频率下,电路功耗仅为68 mW.     

一种轨至轨10位逐次逼近模数转换器的设计

设计了一款用于汽车电子MCU的轨至轨10位逐次逼近A/D转换器。采用单电容采样的DAC结构,保证A/D转换器的全摆幅输入范围。在后仿真验证中,采用频谱分析方法,标定寄生电容对DAC精度的影响,优化了版图结构。设计了片内低压差线性稳压器,提供稳定的电源电压信号。芯片采用GSMC 0.18μm 1P6M CMOS工艺实现。后仿真结果表明,在1.8V电源电压、51kHz输入信号频率、1MHz时钟频率下,无杂散动态范围(SFDR)为73.596dB,有效位数(ENOB)达到9.78位,整体功耗2.24mW,满足汽车电子MCU的应用需求。     

低功耗、全差分流水线操作CMOSA/D转换器

提出一种基于运算跨导放大器共享技术的流水线操作A/ D转换器体系结构,其优点是可以大幅度降低芯片的功耗和面积.采用这种结构设计了一个10位2 0 MS/ s转换速率的全差分流水线操作A/ D转换器,并用CSMC0 .6 μm工艺实现.测试结果表明,积分非线性为1.95 L SB,微分非线性为1.75 L SB;在6 MHz/ s采样频率下,对1.84 MHz信号转换的无杂散动态范围为5 5 .8d B;在5 V工作电压、2 0 MHz/ s采样频率下,功耗为6 5 m W.     

一种10位80 Ms/s逐次逼近A/D转换器

基于65 nm CMOS工艺,设计了一种10位80 Ms/s的逐次逼近A/D转换器。该A/D转换器采用1.2 V电源供电以及差分输入、拆分单调的DAC网络结构。采用拆分单调的电容阵列DAC,可以有效降低A/D转换所消耗的能量,缩短DAC的建立时间,降低控制逻辑的复杂度,提高转换速度;避免了由于比较器共模电平下降过多引起的比较器失调,从而降低了比较器的设计难度,改善了ADC的线性度。动态比较器降低了A/D转换的功耗。使用Spectre进行仿真验证,结果表明,当采样频率为80 MHz,输入信号频率为40 MHz时,该A/D转换器的SFDR为72 dBc。     

一种10位100-MS/s CMOS流水折叠式A/D转换器

采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下：INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。     

一种10位10 MS/s自补偿SAR A/D转换器

基于SMIC 0.18 μm CMOS工艺,设计了一种10位自补偿逐次逼近(SAR)A/D转换器芯片。采用5+5分段式结构,将电容阵列分成高5位和低5位;采用额外添加补偿电容的方法,对电容阵列进行补偿,以提高电容之间的匹配。采用线性开关,以提高采样速率,降低功耗。版图布局中,使用了一种匹配性能较好的电容阵列,以提高整体芯片的对称性,降低寄生参数的影响。在输入信号频率为0.956 2 MHz,时钟频率为125 MHz的条件下进行后仿真,该A/D转换器的信号噪声失真比(SNDR)为61.230 8 dB,无杂散动态范围(SFDR)达到75.220 4 dB,有效位数(ENOB)达到9.87位。     

一个低电压低功耗10位30MS/s流水线A/D转换器

实现了一个10位精度,30MS/s,1.2V电源电压流水线A/D转换器,通过采用运放共享技术和动态比较器,大大降低了电路的功耗。为了在低电源电压下获得较大的摆幅,设计了一个采用新颖频率补偿方法的两级运放,并深入分析了该运放的频率特性。同时还采用了一个新的偏置电路给运放提供稳定且精确的偏置。在30MHz采样时钟,0.5MHz输入信号下测试,可以得到8.1bit有效位的输出,当输入频率上升到60MHz(四倍奈奎斯特频率)时,仍然有7.9bit有效位。电路积分非线性的最大值为1.98LSB,微分非线性的最大值为0.7LSB。电路采用0.13μmCMOS工艺流片验证,芯片面积为1.12mm2,功耗仅为14.4mW。     

一种双采样10位50 MS/s采样保持电路的设计

介绍了一种可以进行双采样的10 位50 MS/s采样保持电路.该电路采用SMIC 0.25 μm标准数字CMOS工艺进行设计.基于BSIM3V3 Spice模型,采用Hspice对整个电路进行了仿真.结果表明,电路在工作于50 MS/s、输入信号频率为25 MHz时,输出信号的SNDR为62.1 dB,整个电路的功耗仅为8.41 mW.     

10-bit 10Ms/S流水线A/D转换器的设计

在现有流水线A/D转换器设计的基础上,应用电荷泵改进了MOS模拟开关的性能,运用宽带运算放大器提高了电路速度,引入底极板采样和数字校正技术来提高精度,采用动态比较器实现较低的功耗.设计实现了一个10-bit 10Ms/S流水线A/D转换器,并以TSMC 0.35 CMOS工艺的Bsim 3v3模型用HSPICE对电路的性能进行仿真验证,结果表明其各项性能均达到预期的设计要求.     

10 Gsample/s optoelectronic A/D converter

A 5 bit, 10 Gsample/s flash A/D converter (ADC) is fabricated for 10 Gbit/s optical receivers. To achieve a 10 Gsample/s rate with wide signal bandwidth, the design focuses on reducing aperture uncertainty, clock skew, and metastability error. The ADC achieves 4.1 effective bits at low input frequencies and 2.8 effective bits at 4.9 GHz input signal at 10 Gsample/s.     

10bit 20MS/s流水线模数转换器设计

设计了一个20MHz采样率,10bit精度流水线模数转换器。采用新颖的栅压自举开关,使电路在输入信号频率很高时仍具有良好的动态性能;用MATLAB仿真增益增强型运算放大器在不同反馈因子下闭环零、极点特性,提出了使大信号建立时间最短的主运放、辅助运放单位增益带宽和相位裕度范围。采用SMIC0.35μm2P4M工艺流片验证,20MHz采样率,2.1MHz输入信号下,SFDR=73dBc,ENOB=9.18bit。     

一种10位乘法型D／A转换器的设计

本文介绍一种采用Ｒ－２Ｒ梯形电阻网络和ＣＭＯＳ模拟开关的典型结构的单片１０位Ｄ／Ａ转换器。在设计和制作上进行优化，不用激光修调能够达到１０位精度，在全温范围内有较高的温度跟踪特性。     

A 10-bit 100 MSamples/s BiCMOS D/A Converter

This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8µm BiCMOS process and is designed to operate at a sampling rate of 100MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5V, and has a power consumption of approximately 650mW. The area of the chip-core is 2.2mm × 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are both approximately 2 LSB. At a generated frequency of f _g0.1 f _s(f _s = 100MSamples/s) the measured SFDR is 50dB, and at f _g0.3 f _s the measured SFDR is as high as 43dB. The DAC is operating up to a sampling frequency of approximately 140MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed. This energy measure is especially useful during the design phase.     

A 10-bit pipelined switched-current A/D converter

A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm² . The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy     

A 10-b 40-Msample/s BiCMOS A/D converter

A fully-differential, 10-b, 40-Msample/s pipelined analog-to-digital converter (ADC) has been developed and tested. The converter exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes <400 mW of power from a single 5 V supply. The converter can digitize not only a fully-differential but also a single-ended input signal over a wide input range with little variation in converter performance. In addition, a full-power bandwidth (FPBW) of >250 MHz is made possible with the open-loop sampling scheme     

A complete monolithic 10-b D/A converter

A monolithic 10-b plus sign D/A converter has been developed that incorporates all necessary circuit functions including voltage reference and internally compensated high-speed output op amp in a single 82/spl times/148 mil chip. A unique logic switch and current source configuration achieves 0.05 percent nonlinearity with /spl plusmn/10 V compliance current output option as well as true or complementary binary coding. The design constraints and area requirements for scaling of current source emitter areas are reduced by using a new active current-splitting technique. The circuit features a 1.5 /spl mu/s settling time voltage output and sign-magnitude coding.     

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.