A Current-Mode based Field-Programmable Analog Array for Signal Processing Applications

This paper presents a new approach to develop Field Programmable Analog Arrays (FPAAs),¹ which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also introduces a novel FPAA architecture, devoid of the conventional switching and connection modules. The proposed FPAA is based on simple current mode sub-circuits. An uncompounded methodology has been employed for the programming of the Configurable Analog Cell (CAC). Current mode approach has enabled the operation of the FPAA presented here, over almost three decades of frequency range. We have demonstrated the feasibility of the FPAA by implementing some signal processing functions.     

A Current Conveyor based Field Programmable Analog Array

An approach for designing a Field Programmable Analog Array (FPAA) is described. The analog array is based on current conveyors and benefits from two major interests: a large bandwidth and a low number of discrete components needed for the implementation of analog functions. An Analog Elementary Cell (AEC), based on current conveyors has been developed, and it is associated with programmable resistors and capacitors. Analog functions can be performed programming several AECs as current-mode amplifiers, analog multipliers, etc. The main purpose of this paper is to introduce current conveyor based analog blocks which are very-well suited for the implementation of FPAA. A particular interconnection architecture is addressed using current conveyors as switches. The major key feature of the proposed approach is that current conveyors are used as active elements and switching elements. A new topology based on the developed AEC is proposed and should be shortly validated.     

基于现场可编程模拟阵列的音频测量滤波器的设计及实现

采用新型的开关电容现场可编程模拟阵列FPAA，完成音频测量滤波器的设计、时域仿真和SPICE频域仿真。以设计、仿真实现高性能的20kHz低通滤波器为例，最后下载到一片FPAA芯片中实现。     

A Switched Capacitor Approach to Field-Programmable Analog Array (FPAA) Design

We present a voltage mode switched-capacitor Field Programmable Analog Array (FPAA) to be used to implement various analog circuits. The FPAA consists of uniform configurable analog blocks (CABs) allowing implementation of different functions. Each CAB consists of two back-to-back connected inverting and non-inverting strays-insensitive switched-capacitor integrators. The interconnection between CABs is implemented by switched and unswitched capacitor networks. The internal structure of CABs and the interconnection between different CABs are configured by user-programmable digital control signals. The functionality of the FPAA is demonstrated through embedding of different types of filters, programmable amplifiers, biquads, modulators and signal generators along with simulation results.     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis

In this work a strategy for testing analog networks, known as Transient Response Analysis Method, is applied to test the Configurable Analog Blocks (CABs) of Field Programmable Analog Arrays (FPAAs). In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks to known input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between fault-free and faulty CABs. Two FPAAs from different manufacturers and distinct architectures are considered as CUT. For one of the devices there is no detailed information about its structural implementation. For this reason, a functional fault model based on high-level parameters of the transfer function of the programmed blocks is adopted, and then, the relationship between these parameters and CAB component deviations is investigated. The other considered device allows a structural programming in which the designer can directly modify the values of programmable components. This way, faults can be injected by modifying the values of these components in order to emulate a defective behavior. Therefore, it is possible to estimate the fault coverage and test application time of the proposed functional test method when applied to both considered devices.

DPAD2—A Field Programmable Analog Array

DPAD2 is a Field Programmable Analog Array (FPAA) based on CMOS switched capacitor technology. This paper describes the major design decisions that went into creating DPAD2 with respect to the ultimate goal of the work, being a mixed signal field programmable silicon solution. Two major compromises exist in the design of an FPAA, one between flexibility and performance, the other between functionality and die size; DPAD2 overcomes the first with a novel field programmable hierarchic routing scheme and the second by careful analysis of many disparate designs to arrive at a best compromise solution. Results from prototype silicon are presented where a single analog cell is reconfigured to perform a number of different analog signal processing functions. Bandwidth of the DPAD2 device is 500 kHz and the SNR is typically 60 dB, although both are application dependent. Introduction of the FPAA now enables a designer to have working silicon within one day, by a simple configuration of the silicon chip via a PC parallel interface. Software libraries of analog circuits are provided and allow very rapid creation of large and complex analog circuits.     

Built-in self-test of global interconnects of field programmable analog arrays

Strategies for the test of Field Programmable Analog Arrays (FPAAs) have been devised based on testing separately their main three components: configurable analog blocks, I/O pads and interconnection network. In this work, a scheme for testing the interconnection network, in particular the global wiring, is presented. As long as analog wiring is considered, catastrophic faults at the switches and wires are considered, as well as parametric capacitive or resistive defects in interconnects. Similarly to FPGAs, critical path search is based on a graph model, so that known algorithms are reused, yielding a minimum number of Test Configurations. Then, a near-zero area overhead BIST procedure is proposed, in which Analog Built-in Block Observers are implemented as oscillators and integrators, respectively, generating test stimuli and analyzing output responses, using internal configurable resources of the FPAA.     

Field programmable analog arrays for implementation of generalized nth‐order operational transconductance amplifier‐C elliptic filters

This study presents a new architecture for a field programmable analog array (FPAA) for use in low‐frequency applications, and a generalized circuit realization method for the implementation of nth‐order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA‐C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA‐C symmetric balanced structure for even/odd‐nth‐order low‐pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90‐nm complementary metal‐oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low‐power designs for implementation of biopotential signal processing systems.     

Filter Design Using a New Field-Programmable Analog Array (FPAA)

We present a voltage mode switched-capacitor Field ProgrammableAnalog Array (FPAA) to be used to implement various filter structures.The FPAA consists of uniform configurable analog blocks (CABs)allowing implementation of different functions. Each CAB consistsof two back-to-back connected inverting and non-inverting strays-insensitiveswitched-capacitor integrators. The interconnection between CABsis implemented by switched and unswitched capacitor networks.The internal structure of CABs and the interconnection betweendifferent CABs are configured by user-programmable digital controlsignals. The functionality of the FPAA is demonstrated throughembedding of different types of filters along with simulationresults.     

一种基于FPGA的直接数字射频上变频方案

传统模拟器件实现射频(RF)上变频方法存在硬件复杂度高,灵活性差,功耗大等缺点。随着半导体器件的发展,软件无线电要求将上变频中射频或中频的信号处理尽量往基带数字信号处理靠拢。本文利用多相滤波器原理,提出一种基于现场可编程门阵列(FPGA)的直接数字RF上变频架构和实施方案,并且通过软硬件仿真验证了该方案的可行性。     

分布式算法在FIR数字滤波器实现中的应用

文章提出了一种利用FPGA实现FIR数字滤波器的设计方案,在设计过程中应用了分布式算法(DA).FPGA有着规整的内部逻辑阵列和丰富的连线资源,特别适合于数字信号处理任务.分布式算法(DA)是一项重要的FPGA技术,它使得在FPGA中实现FIR滤波器的关键运算--乘加运算,转化为了查找表,大大提高了FIR滤波器的速度.文中给出了VHDL语言编写的程序和仿真波形.     

基于FPGA的钢丝绳漏磁无损检测系统设计

提出一种以现场可编程门阵列（FPGA）为硬件核心的钢丝绳漏磁无损检测系统设计方案,设计了外围电路并对嵌入式IP软核进行了配置。利用C语言和VHDL硬件描述语言编写了检测系统软件程序。实验表明该系统具有功耗低、运算能力强、精度高、便于携带等优点。     

Programmable Analog/Digital Arrays in Control and Simulation

This paper presents an investigation of dynamically reconfigurable mixed-signal circuits implementing adaptive controllers and plant simulators. Motorola Field Programmable Analog Array described in this paper are used to build adaptive controllers and plant simulators for predictive control. The reported experimental studies describe performance and programmability of the Field Programmable Analog Array necessary for application in adaptive control and simulation. The experimental structure is based on 2 parallel Field Programmable Analog Array chips, analog multiplexer and multiplexer's control logic, which is steered by a digital system such as a desktop computer or a Field Programmable Gate Array. Dynamic reconfiguration is used in this system for adaptive control or adaptive processing in general. Modeling and measurements of the transitions in the internal blocks of the two Field Programmable Analog Array chips working in parallel, and analysis of limitations resulting from hardware imperfections are presented.     

A Novel Switched-Capacitor Based Field-Programmable Analog Array Architecture

A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).     

CPLD／FPGA的发展与应用之比较

可编程逻辑器件（Programmable Logic Device，PLD）是一种可由用户对其进行编程的大规模通用集成电路。从PLD的发展历程着眼，主要对PLD的2个发展分支——复杂可编程逻辑器件和现场可编程门阵列的基本结构、功能优势和应用场合进行了较详尽的分析和比较；并从结构和定义上指出二者的区别，同时根据不同技术要求和设计环境指出了相应的CPLD和FPGA的选择方法，最后给出了PLD最新研究热点和未来的发展趋势。     

Review of advanced FPGA architectures and technologies

Field Programmable Gate Array （FPGA） is an efficient reconfigurable integrated circuit platform and has become a core signal processing mieroehip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system inte- gration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, intercon- nects, and embedded resources. Moreover, some important emerging design issues of FPGA archi- tectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.     

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS简

Field Programmable Gate Arrays （FPGAs） offer high capability in implementing of com- plex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets （SEUs）. To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.     

基于跨导运算放大器的可重构模拟电路及应用设计

常规的粗粒度可重构模拟电路灵活性不高,而且可重构模拟单元(CAB)结构较为复杂。针对此类问题,该文改进并设计了一种新的基于OTA的可重构模拟电路。该电路设计方案降低了CAB的复杂度,提高了CAB的使用效率。该文方法的有效性通过3个模拟设计实例(二阶低通滤波器、高通滤波器和三阶巴特沃思低通滤波器)的设计加以验证。实验结果表明,所提出的方法正确有效,可以较好地兼顾CAB资源与所要求功能的平衡。     

LabVIEW现场可编程门阵列模块数据采集系统仿真

现场可编程门阵列（FPGA）~数据采集、信号处理、测量控制等领域发挥着越来越重要的作用。目前,美国国家仪器（NI）公司已经将其图形化编程语言LabVIEW的应用扩展到了FPGA开发领域,从而使FPGA的开发变得相对容易和便捷。基于NI公司的CompactRIO系统架构,选用N19205模块,利用仿真技术开发了一套数据采集系统,能够对信号进行采集并分析采集信号的振幅谱和相位谱。该数据采集系统具有一定的实际意义和价值,并可进一步扩展为自动化软件测试平台。