基于异构忆阻器的1T2M多值存储交叉阵列设计

忆阻器作为一种新型电子元件,具有尺寸小、读写速度快、非易失性和易于与CMOS电路兼容等特性,是实现非易失性存储器最具发展前景的技术之一。但是已有的多值存储交叉阵列存在电路结构复杂、漏电流和存储密度低等问题,影响了多值存储交叉阵列的实用性。该文提出一种基于异构忆阻器的多值存储交叉阵列,其中存储单元由1个MOS管和两个具有不同阈值电压和R_on阻值的异构忆阻器构成(1T2M),可实现单个电压信号完成4值读写的操作,减少电流通路的同时简化了电路结构。通过PSpice进行仿真验证,表明所提出的1T2M多值存储器交叉阵列与已有工作相比,电路结构更简单,读写速度更快,并较好地克服了漏电流问题。     

基于异构忆阻器的1T2M多值存储交叉阵列设计

忆阻器作为一种新型电子元件,具有尺寸小、读写速度快、非易失性和易于与CMOS电路兼容等特性,是实现非易失性存储器最具发展前景的技术之一.但是已有的多值存储交叉阵列存在电路结构复杂、漏电流和存储密度低等问题,影响了多值存储交叉阵列的实用性.该文提出一种基于异构忆阻器的多值存储交叉阵列,其中存储单元由1个MOS管和两个具有不同阈值电压和Ron阻值的异构忆阻器构成(1T2M),可实现单个电压信号完成4值读写的操作,减少电流通路的同时简化了电路结构.通过PSpice进行仿真验证,表明所提出的1T2M多值存储器交叉阵列与已有工作相比,电路结构更简单,读写速度更快,并较好地克服了漏电流问题.     

基于忆阻器的感存算一体技术综述

忆阻器的低功耗、高响应、纳米级、非易失性等特性,在实现非冯·诺依曼计算架构中展现出巨大潜力。基于忆阻器的高密度横梁阵列可实现数据存储及并行计算一体的逻辑电路和类脑计算电路。此外,纳米传感器与忆阻器进一步集成,采集的信号直接送往忆阻器阵列进行运算和存储,感知、存储与计算一体化的芯片技术成为新的研究热点。该文对基于忆阻器的存算一体技术、感存算一体技术的研究现状进行综述,并给出研究前景展望。     

基于忆阻器的感存算一体技术综述

忆阻器的低功耗、高响应、纳米级、非易失性等特性,在实现非冯·诺依曼计算架构中展现出巨大潜力.基于忆阻器的高密度横梁阵列可实现数据存储及并行计算一体的逻辑电路和类脑计算电路.此外,纳米传感器与忆阻器进一步集成,采集的信号直接送往忆阻器阵列进行运算和存储,感知、存储与计算一体化的芯片技术成为新的研究热点.该文对基于忆阻器的存算一体技术、感存算一体技术的研究现状进行综述,并给出研究前景展望.     

交叉杆结构忆阻器件的研究进展

忆阻器被认为是除电容器、电感器、电阻器之外的第四种无源器件,具有器件结构简单、操作速度快、功耗小等优点,是具有电阻记忆特性的非易失性的电阻元件。而交叉杆结构忆阻器件作为忆阻器的一种结构,由于其较之其他结构的忆阻器具有结构简单、集成度高、容错性和并行性优良等特性,受到了外界广泛的关注及研究。文章综述了近年来交叉杆忆阻器的兴起和发展现状,阐述了以交叉杆结构为基础的各类忆阻器的制备及应用。     

业界要闻

<正>国内新闻清华大学在支持片上学习的忆阻器存算一体芯片领域取得重大突破日前,清华大学集成电路学院基于存算一体计算范式,创造性地提出适配忆阻器存算一体实现高效片上学习的新型通用算法和架构（STELLAR）,有效实现大规模模拟型忆阻器阵列与CMOS的单片三维集成,通过算法、架构、集成方式的全流程协同创新,研制出全球首颗全系统集成的、支持高效片上学习的忆阻器存算一体芯片。     

基于忆阻器的Simulink模型及其特性分析

忆阻器是纳米级尺寸、非易失性的两端无源性器件,在数据存储、图像处理和模拟神经网络突触等方面有很大的优势。为了研究忆阻器的特性,在理想的忆阻器模型的基础下,搭建了2种不同窗函数的忆阻器Simulink模型。通过Matlab仿真研究了不同的输入激励以及模型的变化对忆阻器的影响,获得了关于忆阻器的许多新特性和一些重要的结果,并与已知的忆容器和忆感器的输入输出特性作了对比,说明忆阻器与忆容器、忆感器具有相似的特性。仿真结果表明忆阻器在应用方面的具有很大的潜力。     

基于双曲函数的通用型荷控忆阻器电路等效模型分析

目前,忆阻器模拟器的研究主要集中在磁控忆阻器,对荷控忆阻器模拟器的研究不多,双曲函数型的荷控忆阻器模拟器也很少涉及。因此,该文提出一种基于双曲函数的通用型荷控忆阻器模拟器。模拟器通过电压-电流的相互转换电路,实现电路中电压和电流信号之间的相互转换,再通过电路中对应的电路模块对产生的信号进行计算,最终得到通用型双曲荷控忆阻器模型。模拟器能够实现双曲正弦、双曲余弦以及双曲正切函数对应的荷控忆阻器模型。通用型双曲函数荷控忆阻器模拟器对应的等效电路,主要由运算放大器、电阻、电容、三极管等基本元件组成。分析模拟器在不同幅值以及不同频率的输入信号下的伏安特性曲线,得出荷控忆阻器模拟器符合记忆元件的基本特性。该文提出的通用型双曲函数荷控忆阻器模型,对忆阻器模型的发展具有一定的参考意义。     

忆阻器在人工神经网络方面的研究应用

忆阻器是一种具有类似突触特性、记忆特性的新型非线性器件,它具有无源性,低耗能,记忆特性以及纳米尺度等特点,因此常用于构建结构简单、权值灵活可调、集成度高的人工神经网络。而人工神经网络是现代信息处理和智能控制领域的一个重要方法,将忆阻器应用于人工神经网络方面将会加速实现人工智能时代的到来。此方面的研究有许多,比如忆阻器实现神经元电路的研究,忆阻器的智能PID控制器等,本文列举概括了忆阻器在人工神经网络方面的研究应用。     

局部有源忆阻器电路及其在HR耦合神经元网络中的应用

该文提出一种新型局部有源忆阻器,使用标准非线性理论分析方法分析其特性,并通过直流伏安特性曲线来证明其局部有源性。此外,将局部有源忆阻器用于模拟生物突触,构建了一个局部有源忆阻突触耦合HR神经元网络。理论分析和数值仿真表明,在局部有源忆阻突触的影响下它能够产生多种放电模式和复杂的混沌行为。最后,实现了该局部有源忆阻突触耦合神经网络的模拟等效电路,并由功率模拟(PSIM)电路仿真验证了数值仿真的正确性。     

Truly Electroforming‐Free and Low‐Energy Memristors with Preconditioned Conductive Tunneling Paths

1S1R (1 selector and 1 memristor) is a laterally scalable and vertically stackable scheme that can lead to the ultimate memristor density for either memory or neural network applications. In such a scheme, the memristor device needs to be truly electroforming‐free and operated at both low currents and low voltages in order to be compatible with a two‐terminal selector. In this work, a new type of memristor with a preconditioned tunneling conductive path is developed to achieve the required performance characteristics, including truly electroforming‐free, low current below 30 µA (potentially <1 µA), and simultaneously low voltage ≈±0.7 V in switching operations. Such memristors are further integrated with two types of recently developed selectors to demonstrate the feasibility of 1S1R integration.     

An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)

The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and inductor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of charge flowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, and hence can be used for non-volatile memory applications. Researchers have been exploring memristors from various perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture for the efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristor aided logic (MAGIC) design style. A Boolean function is first represented as a Binary Decision Diagram (BDD). The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbar architecture with parallel node evaluation where possible. This is the first approach that combines BDD-based synthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-related problems using a slicing architecture. Experimental evaluations on standard benchmark functions show considerable improvement in the solutions.     

Controlling Threshold and Resistive Switch Functionalities in Ag-Incorporated Organometallic Halide Perovskites for Memristive Crossbar Array

Halide perovskites (HPs) can be the effective functional materials for the sneak-path current issue in the memristive crossbar array. Herein, an efficient strategy is proposed to integrate the HPs-based bidirectional threshold and bipolar resistive switches (TS and RS). The resistance change characteristics from volatile threshold to nonvolatile resistive switching are modulated by controlling Ag doping concentration in the MAPbI₃. HPs provide the diffusive condition and the quantity of Ag regulates the radius of its network. A low amount of Ag contributes to weak network with a short lifetime. However, when the amount of Ag increases, the conductive filament becomes more robust, showing a long lifetime. A MAPbI₃:Ag TS with a low Ag content is developed, showing a steep switching slope (1 mV per decade), fast switching speed (< 80 ns), and low off-current (10 nA). And, a MAPbI₃:Ag RS with a high Ag content is developed, showing multilevel storage capability and long retention time (1400 s). Finally, these TS and RS coupled into the 1S-1R integrated component, resulting the development of the maximum crossbar array size to 1.4 × 10¹². This study offers an efficient methodology for tailoring the resistance change characteristics and a promising strategy for practical HPs-based memristive crossbar application.     

六方氮化硼忆阻器的研究进展

六方氮化硼是一种与石墨烯结构相似的材料,以六方氮化硼作为阻变介质层的忆阻器,具有良好的散热性能,不易发生介电击穿,能够实现小尺寸、低功耗和大的开关比;在计算机运算存储研究、人工神经网络和神经形态(即类脑)计算领域有极大的应用前景。文章主要介绍了忆阻器的分类,分析了六方氮化硼忆阻器的阻变机制,综述了六方氮化硼忆阻器的研究现状。最后,指出了六方氮化硼忆阻器当前面临的挑战,并展望了未来的发展方向。     

Current-Sweep Operation on Nonlinear Selectorless RRAM for Multilevel Cell Applications

Bilayer selectorless resistive random-access memories (RRAM) have been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without additional transistor or a selector integration. The bilayer structures, i.e. high-k layer/low-k layer stacks, are highly scalable while suppressing the sneak path currents (SPC) and reading error in the crossbar RRAM array. The nonlinearity (NL) modulation is also investigated by different operating schemes, and a multilevel cell application is demonstrated with the current-sweep method. The results provide additional insights into the development and optimization of bilayer selectorless RRAMs with high nonlinearity, good memory window, and low switching energy (∼ 40 pJ/bit), which enable the high-density storage and low-power crossbar array memory applications.     

基于忆阻器的乘法器电路设计

忆阻器作为一种非易失性的新型电路元件,在数字逻辑电路中具有良好的应用前景。目前,基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究,其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块,设计了一个2位二进制乘法器电路,另一种是结合新型的比例逻辑,即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较,并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器),相比于过去的忆阻乘法器,减少了大量晶体管的使用。     

The Future of Memristors: Materials Engineering and Neural Networks

From Deep Blue to AlphaGo, artificial intelligence and machine learning are booming, and neural networks have become the hot research direction. However, due to the size limit of complementary metal–oxide–semiconductor (CMOS) transistors, von Neumann-based computing systems are facing multiple challenges (such as memory walls). As the number of transistors required by the neural network increases, the development of neural networks based on the von Neumann computer is limited by volume and energy consumption. As the fourth basic circuit element, memristor shines in the field of neuromorphic computing. The new computer architecture based on memristor is widely considered as a substitute for the von Neumann architecture and has great potential to deal with the neural network and big data era challenge. This article reviews existing materials and structures of memristors, neurophysiological simulations based on memristors, and applications of memristor-based neural networks. The feasibility and advancement of implementing neural networks using memristors are discussed, the difficulties that need to be overcome at this stage are put forward, and their development prospects and challenges faced are also discussed.     

Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs

This paper presents a scheme for designing a memristor-based look-up table (LUT) in which the memristors are connected in rows and columns. As the columns are isolated, the states of the unselected memristors in the proposed scheme are not affected by the WRITE/READ operations; therefore, the prevalent problems associated with nanocrossbars (such as the write half-select and the sneak path currents) are not encountered. Extensive simulation results of the proposed scheme are presented with respect to the WRITE and READ operations; its performance is compared with previous LUT schemes using memristors as well as SRAMs. It is shown that the proposed scheme is significantly better in terms of WRITE time and energy dissipation for both memory operations (i.e. WRITE and READ); moreover it is shown that the READ delay is nearly independent of the LUT dimension. Simulation using benchmark circuits for FPGA implementation show that the proposed LUT offers significant improvements also at this level.     

Emergent spiking in non-ideal memristor networks

Memristors have uses as artificial synapses and perform well in this role in simulations with artificial spiking neurons. Our experiments show that memristor networks natively spike and can exhibit emergent oscillations and bursting spikes. Networks of near-ideal memristors exhibit behaviour similar to a single memristor and combine in circuits like resistors do. Spiking is more likely when filamentary memristors are used or the circuits have a higher degree of compositional complexity (i.e. a larger number of anti-series or anti-parallel interactions). 3-memristor circuits with the same memristor polarity (low compositional complexity) are stabilised and do not show spiking behaviour. 3-memristor circuits with anti-series and/or anti-parallel compositions show richer and more complex dynamics than 2-memristor spiking circuits. We show that the complexity of these dynamics can be quantified by calculating (using partial auto-correlation functions) the minimum order auto-regression function that could fit it. We propose that these oscillations and spikes may have similar phenomena to brainwaves and neural spike trains and suggest that these behaviours can be used to perform neuromorphic computation.