A novel fully integrated transmitter front-end with high power-added efficiency

A novel fully integrated transmitter front-end with a simple structure is proposed to obtain both high power-added efficiency (PAE) and a compact RF-front structure. To have all these characteristics, a novel antenna operating as a radiator, a harmonic tuning circuit, and an output matching network of the power amplifier is proposed. Therefore, the direct integration of the output of the power amplifier and antenna can be achieved without any impedance transformers. From the measured results and fabrication, it is shown that the proposed transmitter front-end provides high PAE of 67.5% and compact and integrated RF-front structure by the size reduction of 43% compared with the conventional class-F active antenna for high PAE.     

一种适用于生物电信号处理的全集成五阶Gm-C低通滤波器

传统的Gm-C滤波器OTA输入晶体管大多工作在饱和区,存在输入动态范围较小和跨导值较大等不足,难以满足生物医学电信号处理滤波器所要求的超低截止频率、低功耗与大输入动态范围等要求,采用将输入晶体管钳位到线性工作区的方法,设计了跨导线性可调的OTA以提高滤波器能够处理的信号幅度。并应用该OTA综合了一种五阶Gm-C超低频低通滤波器。仿真结果表明,该滤波器在1.8 V电源,800 m Vpp输入条件下实现了283 Hz的超低低通角频率,-6.4 d B的带内增益,51 d B的三次谐波失真,功耗仅为22μW,适用于可穿戴式生物医学电信号读取电路。     

一个全集成的CMOS脉冲超宽带发射机

本文给出了一个低功耗、全集成的CMOS脉冲式超宽带发射机电路的设计和流片测试结果,其集成了亚纳秒脉冲发生器、脉冲位置调制(PPM)器和天线驱动电路等,可支持多种调制方式并产生最高达1Gp/s的超宽带脉冲序列.设计采用数字驱动信号上升沿触发的新型反馈结构脉冲发生器,可产生稳定的脉冲信号.通过可调的脉冲宽度和PPM调制步长,设计提供了工艺参数和温度变化的补偿手段.     

一种新型雷达通信一体化信号调制解调方法

基于充分利用阵列天线资源,实现雷达与通信信号同时传输的目的,文中提出了一种新型的雷达通信一体化信号调制解调方法。一体化信号的离散频谱是由经特定频率采样的雷达与通信信号的离散频谱交叉形成的。时域上,该一体化信号是由改进的雷达与通信信号相加形成的。文中提出的方法所对应的一体化系统具有许多优点,包括适用的信号形式多样,安全性高,误码率为传统通信模式的一半等。     

A novel 2-D programmable photonic time-delay device formillimeter-wave signal processing applications

We describe a novel programmable photonic true time-delay device that has the properties of low loss, inherent two dimensionality with a packing density exceeding 25 lines/cm², virtually infinite bandwidth, and is easy to manufacture. The delay resolution of the device is on the order of femtoseconds (microns in space) and the total delay exceeds one nanosecond (30 cm in space)     

A fully integrated VCO at 2 GHz

A fully integrated voltage-controlled oscillator at a frequency of 2 GHz with low phase noise has been implemented in a standard bipolar process with a f_t of 25 GHz. The design is based on an LC-resonator with vertical-coupled inductors. Only two metal layers have been used. The supply voltage of the oscillator is 2.7 V. The phase noise is only -136 dB/Hz at 4.7 MHz frequency offset. A tuning range of 150 MHz is achieved with integrated tuning diodes     

A fully integrated digital pulse rate doubler

A new, simple, fully integrated digital pulse rate doubling circuit that requires no passive energy storage elements is reported. The integrated circuit has been realized in a standard bipolar technology using only n-p-n and p-n-p transistors and diffused resistors.     

A fully integrated high-performance FM stereo decoder

A custom FM stereo decoder IC which uses switched-capacitor and linear filters, linear MOS and bipolar circuitry, and digital MOS circuitry to eliminate the requirements for accurate external components and external adjustments is described. The IC includes a combined analog/digital VCO and PLL, a switched-capacitor sine-wave multiplier, and a switched-capacitor pilot detector and cancellation stage. An output S/N ratio greater than 80 dB and output distortion less than 0.1% have been achieved. The part is 26000 mils² and is implemented in a 3 μm n-well CMOS process containing poly-to-poly capacitors, n-p-n's, and ion-implanted poly resistors     

A fully integrated differential impulse radio transmitter

This paper presents a fully integrated differential impulse radio transmitter for ultra-wideband (UWB) applications. The design features low power dissipation, simple hardware, and a precise differential pulse shape. The transmitter employing the time hopping pulse position modulation (TH-PPM) scheme supports eight simultaneous users’ access with 2.5-ns hopping time allocated in a frame time of 20 ns. A differential 5th-derivative Gaussian pulse generator (PG) is designed for the first time to regulate the pulse shape so as to automatically satisfy the Federal Communications Commission (FCC) spectrum mask. The transmitter in a 1.8-V 0.18-μm CMOS process is realized in an IC area of 629 μm × 797 μm for its all digital circuit design. The measured digital pulse width of the TH-PPM pulse train is 2.5 ns and the measured 5th-derivative Gaussian pulse has a peak-to-peak amplitude of 154 mV and a pulse width of 820 ps. The power dissipation of the transmitter is 23 mW.     

A 4th order fully integrated active RC complex filter with novel automatic tuning systems

This letter introduces a 4th order active RC complex filter with 1.5MHz center frequency and 1MHz bandwidth. The total harmonic distortion of the filter is less than –60dB and the image rejection ratio is greater than 60dB. A novel technique is also proposed in this letter to automatically adjust the variation of the time constant. The advantages of the proposed method are its high precision and simplicity. Using 5bits control words, the tuning error is less than ±1.6%.     

A novel finite-element approach to device modeling

A finite-element device-simulation program is presented. An adaptive grid-refinement procedure is used to minimize the number of nodes. Two different kinds of elements are generated (triangles and rectangles) thus enabling the use of an irregular mesh. Different shape functions have been developed for the three variables; they are linear/ bilinear for the electric potential and linear/bilinear in Bernoulli-like functions for the quasi-Fermi potentials. Numerical examples are presented.     

一种新颖全差分光电集成接收机的标准CMOS实现

提出一种新颖的全差分光电集成接收机,它包含了全差分光电探测器和相应的差分接收电路,其中全差分光电探测器的作用是实现入射光信号到全差分光生电流信号的转换.采用特许3.3 V、0.35μm标准CMOS工艺,实现了一种相应的宽带、高灵敏度全差分光电集成接收机.测试结果表明:对于850 nm的入射光,集成全差分光电探测器的差分跨阻前置放大器(TIA)的工作速率可达到500 Mbit/s,而整个光接收机的带宽则达到了1.098 5 GHz;在10-12的误码率条件下,灵敏度可达到-12.3 dBm.     

A fully integrated five-gyrator filter at video frequencies

An experimental single-chip silicon integrated-circuit filter is described for use in color television receivers. It comprises five gyrator resonators operating in the range 4-6 MHz. This chip provides all the selectivity required to separate the sound, luminance, and chrominance components from the composite video signal, and is tuned by a single bias potential applied to the p-n junction capacitors on the chip. The chip replaces an equivalent LC filter of about 20 discrete components (coils, capacitors, and resistors) which are bulky, are relatively expensive, and suffer from the need for individual screening and alignment. The theory of gyrators related to providing fully integrated selectivity at high frequency is outlined. Performance boundaries in terms of Q-factor, frequency setting accuracy, noise, distortion, and temperature are considered. Design aspects are discussed, first for a gyrator and then for the complete experimental filter chip.     

A fully integrated multiband MIMO WLAN transceiver RFIC

A multiple-input/multiple-output (MIMO) transceiver RFIC compliant with IEEE 802.11a/b/g and Japan wireless LAN (WLAN) standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four-path composite beam forming (CBF) system, 15 dB of link margin improvement is obtained. The transceiver was implemented in a 47-GHz SiGe technology with 29.1-mm/sup 2/ die size. It consumes 195 mA in RX mode and 240 mA in TX mode from a 2.75-V supply.     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

A low drift fully integrated MOSFET operational amplifier

A fully integrated MOSFET amplifier with very low drift has been built using standard technology. Input offset voltages as low as 5 /spl mu/V and drift values of this offset voltage less than 0.05 /spl mu/V//spl deg/C are measured.     

A fully integrated CMOS DCS-1800 frequency synthesizer

A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 μm CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 μs, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset     

A class AB CMOS fully balanced signal generator

Mixed-signal ICs benefit greatly from processing fully balanced signals. Real-world signals are single-ended and must be converted on-chip to fully balanced signals. This article discusses a simple, accurate, low power CMOS solution to generating fully balanced signals on-chip. The design does not require common-mode feedback and provides a pin for controlling the common-mode level     

A wide-band tuning system for fully integrated satellite receivers

The building blocks for a low-power tuning system that reduces the phase noise of integrated VCO's are described. The multimodulus prescaler, the phase frequency detector, and the wide-band charge pump have been integrated in a standard bipolar technology with 9-GHz n-p-n transistors and 200-MHz p-n-p transistors. The maximum input frequency of the multimodulus prescaler is 3.2 GHz, the maximum reference frequency of the phase frequency detector is 380 MHz, and the 3-dB bandwidth of the charge pump is 41 MHz at a reference frequency of 300 MHz. The achieved performance enables the use of fully integrated VCO's with relatively high phase noise for reception of satellite digital signals     

A 1.57-GHz fully integrated very low-phase-noise quadrature VCO

A very low-phase-noise quadrature voltage-controlled oscillator is presented, featuring an inherently better figure of merit than existing architectures. Through an improved circuit schematic and a special layout technique, the phase noise of the circuit can be lowered. The circuit draws 15 mA from a 2-V supply. The phase noise is -133.5 dBc/Hz at 600 kHz and the tuning range is 24% wide at a center frequency of 1.57 GHz