视频编码器片上系统集成中软硬件协同设计方法的研究

以视频编码器片上系统的设计为实验对象,提出了一种具有较高层次的软硬件协同设计方法。运用该方法着重对视频编码器芯片上ＲＩＳＣ核进行设计,并采用０．３５μｍＣＭＯＳ工艺ＥＤＡ工具上实现。综合结果表明,在系统层次上展开系统芯片的软硬件协同设计,具有具体结构对算的适应性好,设计周期短,系统易于优化等优点。     

新一代RISC微处理器的技术特征与趋向

从流水线技术，指令调度技术，Ｃａｃｈｅ设计技术及多媒体支持等方面详细讨论新一代ＲＩＳＣ微处理器的技术特征，并简要论述ＲＩＳＣ微处理器的发展趋向。     

支持多媒体技术的IBM和Sybase公司

支持多媒体技术的ＩＢＭ和Ｓｙｂａｓｅ公司Ｓｙｂｔ１ＳＣ和ＩＢＭ公司将支持包括以ＩＢＭＰｏｗｅｒＰＣ芯片技术为基础的、新的Ｍｏｄｅｌ２５０机器在内的ＲＩＳＣＳｙｓｔｓｌｌｌ／６０００工作站的多媒体解决办法。ＩＢＭ将综合一套交互式的多媒体示范应用程序，提...     

C80SDB的开发及应用

１Ｃ８０简介Ｃ８０是第一代单片阵列式结构的高级ＤＳＰ芯片，是ＴＩ公司推出的以ＤＳＰ方式工作的高性能多媒体视频处理器，它包括４个先进的并行数字信号处理器（ＡＤＳＰ）和一个精减指令集计算机（ＲＩＳＣ）处理器。此外，片内还有共享存储器，传输控制器（ＴＣ），...     

PA—RISC微处理器PA7100LC的结构设计与多媒体支持

ＰＡ７１００ＬＣ微处理器是ＨＰ公司推出的工作站用ＰＡ－ＲＩＳＣ系列微处理器的成员之一，它的结构设计优化了性能价格比并支持多媒体处理，部分地反映了现代ＲＩＳＣ微处理器的发展趋向。本文将详细介绍ＰＡ７１００ＬＣ微处理器的结构设计及其特征，并讨论它对多媒体处理的支持。     

基于边界扫描的微处理器功能测试算法

针对实现了边界扫描可测试性设计的微处理器的特点,提出了一种改进的微处理器功能测试算法。应用该算法我们成功地完成了３２位ＲＩＳＣ芯片ＬＳ８５３２Ａ的测试。     

Alpha21164微处理器探秘

该文从的角度出发，揭示了当今世界处理速度最快的Ａｌｐｈａ２１１６４微处理器技术，分析了该芯片的微结构，超级流水线结构及指令执行等先进ＲＩＳＣ设计技术。     

RISC工作站的Cache设计

Ｃａｃｈｅ技术是改善计算机系统性能的最重要和最有效的手段之一。近年来兴起的ＲＩＳＣ结构更扩大了Ｃａｃｈｅ技术应用领域。在ＲＩＳＣ系统中，整机性能与处理器对内存的有效访问直接相关，从而使得Ｃａｃｈｅ也更为重要。本文对ＲＩＳＣ系统Ｃａｃｈｅ设计中的许多问题进行讨论，并给出华胜４０００系列ＲＩＳＣ工作站的Ｃａｃｈｅ设计作为实例。     

基于寄存器优化的图象中低层处理

提出了一种在高性能ＲＩＳＣ芯片上进行图象中低层处理的寄存器优化方法,使用该方法能够处理速度提高将近一倍,在ＴＭＳ３２０ｃ４０上所做的实验表明应用该方法能取得较好的效果。     

嵌入式处理器中的慢总线技术应用

提出一种嵌入式处理器“慢总线技术”,采用状态机描述总线接口时序,用软件实现与外围硬件的总线接口互操作。并以嵌和试ＲＩＳＣ微控制器芯片（ＰＫＣ１６Ｃ５４）为例,描述了对ＤＴＭＦ编／（解码芯片（ＭＴ８８０８）接口访问的实现方法。     

多媒体芯片上RISC核的设计研究

多年来,我国无论军用、民用的地形图基本上均为印刷的纸地图,方便的电子地图则很少应用,而信息量大可视性好的地理信息使用的单位更少。主要原因是地理信息系统在我国虽取得了一些进展,有部分专用性地理信息系统投入使用,但在许多领域当中的应用尚处于起步发展阶段,...     

The D30V/MPEG multimedia processor

MPEG-2 decoding and encoding are important applications for multimedia systems. Real-time capability and low-cost implementation are the main design considerations for these systems. Due to the high computational requirements of real-time applications, multimedia systems typically use special-purpose processors to handle data. However, due to the inherent inflexibility of their designs, these dedicated processors are of little use in various application environments-digital videocassette recorders, for example. This article introduces Mitsubishi's D30V/MPEG multimedia processor, which integrates a dual-issue RISC with minimal hardware support for a real-time MPEG-2 decoder. This approach is advantageous because of the small chip area it requires and the flexibility of the easy-to-program RISC processor for multimedia applications     

S3C6410X(ARM11)精简指令系统微处理机(RISC Microprocessor)的特点和使用实例

S3C6410X精简指令系统微处理机是韩国三星电子公司(Samsung Electronics Co.,Ltd)最新推出的内核为ARM11的RISC嵌入式微处理器,ARM11是为了更有效的提高处理器能力而设计的。ARM11处理器以消费产品市场为目标,推出了许多新的技术,包括针对多媒体处理的SMID(Single instruction Multiple Data单指令多数据流),用以提高安全性能的TrustZone(通过硬件和软件结合,为片上数据提供安全环境)技术,智能能源管理IEM(In-Ear Monitoring耳内监听)等,本文对S3C6410X的功能作简单描述并通过一个应用实例介绍如何应用。     

UltraSparc I: a four-issue processor supporting multimedia

UItraSpare I is a second-generation superscalar processor. It is a high performance, highly integrated, four issue superscalar processor based on the Spare Version 9 64-bit RISC architecture. We have extended the core instruction set to include graphics instructions that provide the most common operations related to two dimensional image processing; two- and three-dimensional graphics and image compression algorithms; and parallel operations on pixel data with 8-, 16-, and 32-bit components. Additional, new memory access instructions support the very high bandwidth requirements typical of graphics and multimedia applications     

SH3: high code density, low power

Hitachi's SH series microprocessors feature 32-bit RISC architecture with a 16-bit, fixed-length instruction set. We describe SH3, a pipelined implementation of the SH architecture with on-chip cache, MMU, and software-programmable power management. Its higher code density and corresponding improvement in instruction-fetch latency lead to higher performance than typical 32-bit RISC architectures achieve. These features, small die size, and low power consumption make SH3 an ideal microprocessor for portable computing systems or multimedia systems     

一种RISC地址产生器生成算法的设计与实例化

提高功能部件的并行性是开发高性能微处理器的基本途径。在RISC处理器中设计独立的地址产生器可实现算术运算与地址运算并行处理,从而提高RISC处理器的性能。文中根据现今RISC处理器中常用的寻址方式,提出了一种RISC地址产生器生成算法并进行了实例化。实例化结果可作为IP核应用到RISC处理器的设计中。     

A cost-effective RISC/DSP microprocessor for embedded systems

Applications in telecommunications or multimedia require a new generation of fast and flexible microprocessors. We present a 32-bit RISC microprocessor with extended functionality for digital signal processing that reduces overall system cost. Due to its optimized design with just 210,000 transistors, this low-cost, medium- to high-performance microprocessor is well suited for a wide range of embedded system applications     

A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities

This paper presents the design and the implementation of a coarse-grain reconfigurable machine used as an accelerator for a programmable RISC core, to speed up the execution of computationally demanding tasks like multimedia applications. We created a VHDL model of the proposed architecture and implemented it on a FPGA board for prototyping purposes; then we mapped on our architecture some DSP and image processing algorithms as a benchmark. In particular, we provided the proposed architecture with subword computation capabilities, which turns out to be extremely effective especially when dealing with image processing algorithms, achieving significant benefits in terms of speed and efficiency in resource usage. To create the configuration bitstream (configware) we created a tool based on a graphical user interface (GUI) which provides a first step towards the automation of the programming flow of our design: the tool is meant to ease the life of the programmer, relieving him from the burden of calculating the configuration bits by hand. Synthesis results indicate that the area occupation and the operating frequency of our design are reasonable also when compared to other similar design. In addition to this, the amount of clock cycles taken by our machine to perform a given algorithm is orders of magnitude smaller than the one required by a corresponding software implementation on a RISC microprocessor.     

基于双处理器图像采集与处理的同步

OMAP系列是TI公司针对第三代手机而开发的高性能多媒体处理器，集成有一个ARM的内核和一个DSP的内核(TMS320C55x)。本文设计了OMAPl510和OV7640的接口电路。采用非常简单的机制，实现了ARM处理器采集图像与DSP视频编码的同步，该方案可广泛应用在采用双处理器分别进行图像采集和压缩的硬件平台上。