A new model for the post-stress interface trap generation inhot-carrier stressed p-MOSFETs

A new insight into the post-stress interface trap (N_it) generation in hot-electron stressed p-MOSFETs is presented. N_it generation is suppressed for positive oxide field but enhanced for negative oxide field. This observation provides strong support for a two-carrier model, involving the recombination between trapped electrons and inversion holes. While post-stress interface instability has generally been associated with hole trapping and hydrogen transport, our results clearly show the importance of electron traps on the long term stability of the Si-SiO₂ interface, and that the two-carrier model provides a consistent explanation for post-stress N_it generation in p-MOSFETs stressed under hot-electron injection     

On the mechanism for interface trap generation in MOS transistorsdue to channel hot carrier stressing

The classical concept and theory suggest that the degradation of MOS transistors is caused by interface trap generation resulting from “hot carrier injection.” We report three new experiments that use the deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection. These experiments show clearly that hot carrier injection into the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for standard hot carrier stressing     

Profiling interface traps in MOS transistors by the DCcurrent-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10¹¹ traps/cm² generated by channel hot electron stress     

下一代CMOS IC--双栅极MOS晶体管

IC业人士普遍认为,3、5年内,CMOS IC会达到在一块芯片上集成1亿支MOS晶体管的水平.到2006年,利用0.10～0.13 μ m光刻技术生产的CMOS逻辑IC将会在先进的半导体工厂流片.据分析,这种IC MOS晶体管的典型工艺参数和技术参数将是:沟道长度0.05μm;栅氧化层厚度1～2nm;阈值电压0.25V;电源电压1.2V.根据现有的IC基本知识,这已接近IC技术的基本极限.在基本极限附近,传统的MOS晶体管性能会劣化,例如泄漏电流和静态功耗会显著增加,严重影响IC的正常工作.     

On the punchthrough phenomenon in submicron MOS transistors

As the channel length of MOS transistors reduces to the submicron dimension, the punchthrough becomes more of a surface-initiated and gate-controlled phenomenon. A surface diffusion current (I_sdif) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending (Δφ_so). The DIBL effect increases rapidly with decreasing channel length. In addition, the extracted Δφ_so from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long submicron devices (≈0.62 μm) to the strong-inversion mode for deep submicron devices (≈0.12 μm). In general, I_sdif dominates over the low drain bias range and eventually converts to the bulk space-charge-limited current (I_scl) as the drain bias increases and the source/drain depletion regions connect. The drain bias for this conversion to occur strongly depends on the channel dimension. Only intermediate submicron devices (≈0.37 μm) in this study clearly show both the surface and bulk (space-charge-limited) punchthrough components. For long submicron devices, I_sdif essentially dominates, while for deep submicron devices, it converts rapidly to I_scl over the drain bias range investigated. A semi-empirical closed form equation is proposed to describe both I_sdif and I_scl and their merging over the entire range of drain bias     

On the I-V characteristics of floating-gate MOS transistors

The effects of capacitive coupling on the I-V characteristics of floating-gate MOS transistors are described. A set of modified IV equations for these devices is presented and compared with experimental results.     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

Evidence of optical generation of minority carriers from saturated MOS transistors

Minority carrier injection into the substrate by a MOS transistor operating in saturation presents a reliability problem in dynamic memory circuits such as RAM's and CCD's. The effect has been studied by measuring the substrate and drain currents of stressed transistors as a function of gate and drain voltages, firstly by the accumulation of minority carriers in a charge coupled device, and secondly by the direct detection of light from the drain region of a transistor. These results suggest that light emission associated with multiplication in the drain region is more important than the secondary impact ionization mechanism in the generation of minority carriers.     

Donor-like interface trap generation in pMOSFET's at roomtemperature

The generation of donor-like interface traps under room temperature bias stress is observed. This generation process is insensitive to the gate polarity, hot carrier stress, and positive charge formation in the gate oxide. It requires the simultaneous presence of boron- and water-related species. The generated interface traps are nonuniformly distributed along the channel     

On the origin of leakage currents in silicon-on-sapphire MOS transistors

n-channel n-p-n metal-oxide-semiconductor transistors (MOST's), fabricated in thin films of silicon-on-sapphire, exhibit values of source-to-drain leakage currents (IL)which vary from wafer to wafer, typicaily from 10^-11to 10^-7A/mil of channel width. Conversely, p-channel (p-n-p) devices exhibit low leakage current values in the range of 10^-11∼ 10^-10A/mil of channel width, consistent from wafer to Wafer. A model of a high concentration of donorlike states in the silicon in the vicinity of the Al2O3-Si interface creating a back-surface Conductive channel is proposed to account for both the inconsistently high n-channel and consistently low p-channel leakage current values. Experimental measurements of IL, which support the general conclusions of the model, are presented. ILis shown to be a strong function of a) the annealing temperature of the sapphire substrate prior to film growth, b) the silicon-film growth rate, c) the impurity concentration profile in the channel region, and d) the device geometry. These measurements show that the dominant factor controlling the overall magnitude of ILis the state of the Al2O3-Si interface immediately prior to silicon-film growth. A set of silicon-film growth conditions and device processing steps is outlined which achieve consistent n- and p-channel leakage current values of less than 10^-9A/mil of gate width.     

Single transistor technique for interface trap density measurement in irradiated MOS devices

The effect of interface trap charge variation during measurement of the MOSFET current–voltage characteristic has been examined. Taking into account this effect, an interface trap density extraction technique is proposed. The transconductance degradation in this technique is caused not only by channel mobility decrease, but also by I_d(V_g) curve distortion due to interface trapped charge variation during measurement. The analytical and numerical models for the effect are developed. The experimental data on channel mobility and interface trap density vs total dose are shown.     

Spectroscopic charge pumping: A new procedure for measuringinterface trap distributions on MOS transistors

An approach to the application of the charge pumping technique is proposed as a tool for the measurement of interface trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the interface-trap distribution is slowly varying with energy and that the trap capture cross section is nearly constant over energy and temperature     

Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

Defect structure and generation of interface states in MOS structures

The correlation between the defect structure of the SiO₂ and the generation of interface traps upon avalanche injection of electrons and holes in MOS capacitor was investigated. Using samples with widely varying densities of intrinsic and H₂O-related trapping centers, and with different oxide thicknesses and gate electrodes it was established from experiments around room temperature that a one to one correlation between the densities of captured carriers and generated interface states exists as long as only a single type of carrier is involved. If simultaneously the second type of carrier is injected the picture becomes more complex. We confirm reports by other authors that at reduced temperatures (typically 77 K) two steps may be distinguished in the generation process, one of which is thermally activated. In this case the “yield” of interface states drops to values distinctly below one, even after warm up. In many cases the energy distribution of the states shows characteristic features: at E = E_v + 0.45 eV for electron injection in samples with H₂O related traps, at E = E_v + 0.75 eV for hole injection. Samples exhibiting these features always show the occurrence of slow states.     

Characterization of interface trap dynamics responsible for hysteresis in organic thin-film transistors

In this paper, the current hysteresis of organic thin film transistors (OTFTs) formed by TIPS-Pentacene has been demonstrated by bi-directional gate-voltage scan and explained using the trapping and detrapping mechanism. The trapping and detrapping rates have been further verified by the gate-voltage sampling method and the channel charge pumping method. The validity of the methods to characterize interface states of OTFTs that lead to the hysteresis is justified. The two independent methods consistently reveal that the hole trapping and release rates at the interface between the channel of the OTFTs to the gate dielectric are asymmetric.     

Theory of transient emission current in MOS devices and the direct determination interface trap parameters

The physics is discussed of the emission of electrons from interface states in metal-insulator-semiconductor (MIS) systems, under isothermal, non-steady-state conditions. Generalized equations are then derived which permit the determination of the non-steady-state, emission current vs time characteristics for MOS systems containing an arbitrary distribution of surface states; the special case of a discrete surface state is also studied. More important, however, by appropriate plotting of the data, it is shown how to directly extract from the experimental data the energy distribution and the capture cross section of the interface traps in the upper-half of the band gap in the case of n-type semiconductors, and in the lower-half of the band gap in the case of p-type semiconductors.     

Transient isothermal generation at the silicon-silicon oxide interface and the direct determination of interface trap distribution

The theory of transient isothermal generation through the interface traps at the semiconductor-insulator interface is presented. The generation current (I_g) vs time (t) characteristic is obtained in terms of the interface trap distribution throughout the bandgap. It is shown that a plot of I_et vs log_et is a direct image of the energy distribution of the traps in the upper-half of the bandgap (in the case of an n-type semiconductor) and a plot of I_gt vs log_et is a direct image of the trap distribution in the lower-half of the bandgap.     

Localized interface trap generation in SILO-isolated MOSFETs duringPECVD nitride passivation

The authors report the generation of interface traps during the plasma-enhanced chemical vapor deposition of silicon nitride passivation in MOS structures that utilize a sealed-interface local oxidation scheme (SILO) for device isolation. These traps are highly localized at the boundaries between gate and field oxides, causing enhanced subthreshold conduction. Localized interface traps of this type were not observed in identical MOS structures that use conventional LOCOS (local oxidation of silicon) isolation and were eliminated by thermal anneals at 450°C. Anneals in hydrogen ambients resulted in enhanced rates of hot-carrier-induced degradation. The high densities and localized nature of these anomalous traps make possible a novel mode of device operation in which source-drain conduction is strongly modulated by substrate bias