蓝牙组合生成器相关系数的计算方法

蓝牙组合生成器是蓝牙协议中使用的密钥流生成算法,它是一个带4 bit记忆的非线性组合生成器,其输入和输出之间相关系数的表示和计算是一个困难的问题,而这是对这种生成器进行相关性分析和相关攻击的基础.该文对一般的带记忆组合生成器给出了相关系数和条件相关系数的计算公式,该公式易于实现快速计算.基于此公式计算了蓝牙组合生成器的各种相关系数,并列出了部分结果.     

Correlation properties of combiners with memory in stream ciphers

For pseudo-random generators where one or several LFSRs are combined by a memoryless function, it is known that the output sequences are correlated to certain LFSR-sequences whose correlation coefficients c _t satisfy the equation _i c ₂ ⁱ = 1. In this paper it is proved that a corresponding result also holds for generators whose LFSRs are connected to a combiner with memory.If correlation probabilities are conditioned on side information, e.g., on known output digits, it is shown that new or stronger correlations may occur. This is exemplified for the summation cipher with only two LFSRs where such correlations can be exploited in a known plaintext attack. A cryptanalytic algorithm is given which is shown to be successful for LFSRs of considerable length and with arbitrary feedback connection.A preliminary version of this paper was presented at Eurocrypt '90, May 21–24, Århus, Denmark, and has appeared in the proceedings, pp. 204–213.     

无记忆组合函数的非线性与相关免疫性

本文探讨了无记忆组合函数的非线性与相关免疫性之间的关系，利用Ｗａｌｓｈ交换，研究了广义相关免疫函数的频谱特征，并且讨论了Ｂｅｎｔ函数的广义相关免疫阶数。     

流密码中非线性组合函数的分析与设计

从互信息的观点出发，本文研究了非线性组合函数与其部分变量的组合之间的相关性，探讨了这种相关性对流密码安全性的影响。利用Ｗａｌｓｈ变换，分析了Ｂｅｎｔ函数与其部分变量之间的相关性，给出了一类与Ｂｅｎｔ函数有相同渐近谱特性的布尔函数的结构。     

Maximum Correlation Analysis of Nonlinear Combining Functions in Stream Ciphers

The maximum correlation of a Boolean function to all Boolean functions of a subset of its input variables is investigated. A relationship is derived between the maximum correlation and the mutual information between the output of a balanced Boolean function and a subset of its random input variables. For bent functions (which are never balanced), both the mutual information and the maximum correlation are bounded and shown to be small in a strong sense. Received 14 February 1996 and revised 15 January 2000 Online publication 19 May 2000     

Security Analysis of A Stream Cipher with Proven Properties

Si and Ding proposed a stream cipher with two keys (the first and the second key) and an expected security strength. To further measure the security, we analyze the stream cipher by considering the selective discrete Fourier spectra attack and the fast selective discrete Fourier spectra attack. The two attacks reveal a fact that the second key is more important than the first key, that is, if the second key is leaked out, the first key can be obtained with a lower time complexity than that of the expected security. In addition, we analyze the ability of the stream cipher to resist the guess-and-determine attack. The results show an attacker is able to gain the two keys with an exponentially improved time complexity and a polynomial data complexity. It implies that we need a securer permutation over finite fields to design a new binary additive stream cipher to achieve the expected security level.     

不同E_b/N_0条件下误码性能测试

对数字卫星通信系统中Eb/N0与(C0+N0)/N0的关系进行了详细分析,并给出了二者之间的转换公式,在此基础上,将Eb/N0与误码率间的关系转化为(C0+N0)/N0与误码率间的关系。最后给出了(C0+N0)/N0和误码率测试的方法和测试中的注意事项。     

Feedback shift registers, 2-adic span, and combiners with memory

Feedback shift registers with carry operation (FCSRs) are described, implemented, and analyzed with respect to memory requirements, initial loading, period, and distributional properties of their output sequences. Many parallels with the theory of linear feedback shift registers (LFSRs) are presented, including a synthesis algorithm (analogous to the Berlekamp-Massey algorithm for LFSRs) which, for any pseudorandom sequence, constructs the smallest FCSR which will generate the sequence. These techniques are used to attack the summation cipher. This analysis gives a unified approach to the study of pseudorandom sequences, arithmetic codes, combiners with memory, and the Marsaglia-Zaman random number generator. Possible variations on the FCSR architecture are indicated at the end. Andrew Klapper was sponsored by the Natural Sciences and Engineering Research Council under Operating Grant OGP0121648, the National Security Agency under Grant Number MDA904-91-H-0012, and the National Science Foundation under Grant Number NCR9400762. The United States Government is authorized to reproduce and distribute reprints notwithstanding any copyright notation hereon. Mark Goresky was partially supported by the Ellentuck Fund and National Science Foundation Grant Number DMS 9304580.     

具有1比特记忆的组合器的相关性

探讨了具有1比特记忆的组合器的输出序列和输入序列的相关性以及记忆对相关性的影响。     

32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

一种E类驱动单级式电子镇流器的仿真研究

提出了一种E类驱动结构的谐振式电子镇流器,将E类结构和buck-boost功率因数校正结构整合成一种单级式电子镇流器。由于E类驱动式的谐振电路只需一个开关管,经过整合后的电路也只需一个控制电路和一个开关管,进一步降低了镇流器的成本提高了效率。文章分析了E类镇流器电路工作在最佳情况下的工作状态,仿真采用脉宽调制控制电路工作。     

1394-VXI零槽控制器模件设计和实现

阐述了基于IEEE1394总线的VXI零槽扩展基器件的基本原理,给出了1394／VXI零槽控制器的逻辑结构、软硬件设计和实现过程。试验结果表明该系统可以稳定地工作,能够和HP系列的VXI总线设备进行互连和集成。     

集UART与RS232于一体的MAX3110E原理及应用

MAX3110E是MAXIM公司推出的全功能收发器 ,它内部包括一个兼容SPITM/MICROWIRETM 接口的UART以及内置电泵电容和±15kVESD保护的双RS-232收发器。该芯片集成度高 ,使用灵活 ,性能优越。文中详细介绍了MAX3110E的特点、原理及应用电路。     

16路E1信号映射芯片TXC-04216的原理与应用

TXC-04216是TRANSWITCH公司生产的E1信号异步映射专用芯片,可以将16路E1信号异步以TU-12方式映射进入用STM-1的一个多片断,字节并行的SDH电信总线,用于光同步数字序列SDH中。本文介绍该器件的功能特性和内部结构,并给了实际应用电路框图。     

双E1接口MPEG2码流传输卡的设计与实现

本文采用FPGA与微控制器相结合的方式,给出了一套双E1接口的MPEG2码流传输卡的软、硬件设计,该设计的特点是设计灵活、价格低廉、功能多样.     

一种节省存储量的SOVA子译码器IP核的设计

在简单分析SOVA译码算法的基础上,对SOVA子译码器IP核的设计进行了整体分析;从硬件实现的角度,对译码算法的特征进行了理论分析,得到了对称状态节点的软信息具有确定关联的结论;并据此优化了硬件设计,极大地减少了存储资源的占用。同时,采用其他两种减少存储空间的优化设计方案和流水线策略,进一步减少了SOVA子译码器的功耗。对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明,文章提出的优化方案可行、有效,极大地降低了硬件资源占用和功耗。     

用0-等效电路分析常规网络的突变与守恒

在电路分析中,电荷守恒和磁链守恒常被用于换路瞬间电容电压和电感电流的突变问题,因为只涉及0-与0 两个时刻,可称之为状态分析,实际上反映的是系统电荷或磁链的连续性问题.本文导出了常规网络电荷守恒和磁链守恒的条件,并就守恒与不守恒两种情况利用0-等效电路的模型进行过程分析,最后证明了不守恒的差额恰好满足更大系统的守恒.     

Design of a Class E Power Amplifier with LDMOS in Standard CMOS

This paper describes the development of a high-voltage transistor in a standard 0.35 μm CMOS technology and its application on a class E power amplifier for mobile communications. The use of a higher voltage already available in the battery has the benefit of reducing the electromigration constrains and having lower voltage drops in the interconnects due to the use of a lower current.Measured results on the active device and simulation show that is possible to achieve a higher power added efficiency using a lateral double diffused MOS, while reducing the current draining the battery.João Ramos (S’02) was born in Angola, in 1974. He received the Licenciatura degree in Electrical Engineering and Computer Science from Instituto Superior Técnico, Lisbon, Portugal.Currently, he is a research assistant at the ESAT-MICAS group of the Katholieke Universiteit Leuven. He is working towards a Ph.D. degree on RF CMOS Power Amplifiers. For this work, he obtained a scholarship from the FCT, Portugal.Michiel S.J. Steyaert (S’85–A’89–SM’92–F’03) was born in Aalst, Belgium, in 1959. He received the M.Sc. degree in electrical-mechanical engineering and the Ph.D. degree in electronics from the Katholieke Universiteit Leuven (KU Leuven), Heverlee, Belgium, in 1983 and 1987, respectively.From 1983 to 1986, he was a Research Assistant with the Laboratory ESAT at KU Leuven, funded by an IWNOL fellowship (Belgian National Foundation for Industrial Research). In 1987, as an IWONL Project Researcher, he was responsible for several industrial projects in the field of analog micropower circuits with the Laboratory ESAT. In 1988, he was a Visiting Assistant Professor at the University of California, Los Angeles. In 1989, he was a Research Associate appointed by the National Fund of Scientific Research (Belgium); in 1992, he was promoted to a Senior Research Associate, and in 1996, he became Research Director at the Laboratory ESAT, KU Leuven. Between 1989 and 1996, he was also a part-time Associate Professor. He is currently a Full Professor at the KU Leuven. His current research interests include high-performance and high-frequency analog integrated circuits for telecommunication systems and analog signal processing.Prof. Steyaert received the European Solid-State Circuits Conference Best Paper Award in 1990 and 2001. He received the 1991 and the 2000 NFWO Alcatel-Bell-Telephone Award for innovative work in integrated circuits for telecommunications. In 1995 and 1997, he received the IEEE-ISSCC Evening Session Award, and the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award.     

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocating memory space but inducing large silicon area and power consumption as well. We first review the existing solutions and propose a three-level memory hierarchy with line-pixel-lookahead to improve access efficiency. Three-level memory hierarchy includes registers, content/slice SRAM and external frame DRAM. We emphasize the need to consider the secondary hierarchy, content/slice SRAM, during the design of an H.264/AVC decoder. Specifically, we introduce a slice SRAM and line-pixel-lookahead to lower the memory capacity and external bandwidth. This SRAM stores neighboring pixels and prevents the data re-access from DRAM. Line-pixel-lookahead exploits multi-dimensional pixel locality so as to averagely improve prediction performance by 6.54% compared to conventional vertical prediction. Simulation results also reveal that the proposal makes a better trade-off between memory allocation and external bandwidth as well as power, leading to 50% of memory power reduction compared to the design without exploiting the secondary slice SRAM hierarchy.