Improvement on the dynamical performance of a power bipolar static induction transistor with a buried gate structure

The failure of a bipolar static induction transistor(BSIT) often occurs in the transient process between the conducting-state and the blocking-state,so a profound understanding of the physical mechanism of the switching process is of significance for designing and fabricating perfect devices.The dynamical characteristics of the transient process between conducting-state and blocking-state BSITs are represented in detail in this paper.The influences of material,structural and technological parameters on the dynamical performances of BSITs are discussed. The mechanism underlying the transient conversion process is analyzed in depth.The technological approaches are developed to improve the dynamical characteristics of BSITs.     

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.     

A novel double-trench LVTSCR used in the ESD protection of a RFIC

A low-voltage triggering silicon-controlled rectifier(LVTSCR),for its high efficiency and low parasitic parameters,has many advantages in ESD protection,especially in ultra-deep sub-micron(UDSM) IC and high frequency applications.In this paper,the impact factors of the snapback characteristics of a LVTSCR and the configuring modes are analyzed and evaluated in detail.These parameters include anode series resistance,gate voltage,structure and size of devices.In addition,a double-trench LVTSCR is presented that can increase the hold-on voltage effectively and offers easy adjustment.Also,its snapback characteristics can obey the ESD design window rule very well.The strategy of ESD protection in a RFIC using a LVTSCR is discussed at the end of the paper.     

超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究

The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.     

Understanding the failure mechanisms of microwave bipolar transistors caused by electrostatic discharge

Electrostatic discharge(ESD) phenomena involve both electrical and thermal effects,and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability.Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors(BJTs) under ESD conditions has been investigated theoretically and experimentally.100 samples have been tested for multiple pulses until a failure occurred.Meanwhile,the distributions of electric field,current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici.There is a good agreement between the simulated results and failure analysis.In the case of a thermal couple,the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects.The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure.When the ESD level increased to 1.3 kV,the collector-base junction has been burnt out first.The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic.In addition,fatigue phenomena are observed during ESD testing,with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded.     

Photoluminescence and heterojunction properties of ZnSxSe1-x Epitaxial layers on GaAs and Ge Grown by organometallic CVD

Epitaxial layers of ZnS_xSe_1-x ranging in thickness from 0.1 μm to 4 μm were grown on GaAs and Ge substrates by a low temperature, low pressure organometallic CVD process. The admixture of small amounts of sulfur to ZnSe results in an improved lattice match with the substrate wafers. The exact lattice match occurs at a composition of x = 0.052 for GaAs and x = 0.035 for Ge. The reduction of the stress at the interface leads to improved photoluminescence properties, as expressed in the narrowing of the width of the near-bandgap peak and in a decrease in the intensity of the self-activated luminescence. The performance of n-ZnSe/p-GaAs heterojunctions is also discussed.     

Influences of Resistor-Type Superconducting Fault Current Limiter on Power System Transient Stability with Asymmetrical Short-Circuit Faults

The transient stability of a single machine to infinite-busbar power system with resistortype superconducting fault current limiters （SFCL） is analyzed under asymmetrical short-circuit fault conditions. The SFCL is considered to introduce a resistance into the three-phase circuits when faults occur. Based on the power-angle curves for different short-circuit conditions of the single-line to ground, double-line to ground and line to line short-circuit faults, the influences of the SFCLs on transient stability are analyzed in detail. The time-domain simulation of transient stability is carried out to verify the analytical results.     

Collinear phase-matching study of terahertz-wave generation via difference frequency mixed in GaAs and Inp

The collinearly phase-matching condition of terahertz-wave generation via difference frequency mixed in GaAs and InP is theoretically studied. In collinear phase-matching, the optimum phase-matching wave hands of these two crystals are calculated. The optimum phase-matching wave bands in GaAs and lnP are 0.95-1.38μm and 0.7-0.96μm respectively. The influence of the wavelength choice of the pump wave on the coherent length in THz-wave tuning is also discussed. The influence of the temperature alteration on the phase-matching and the temperature tuning properties in GaAs crystal are calculated and analyzed. It can serve for the following experiments as a theoretical evidence and a reference as well.     

Collinear phase-matching study of terahertz-wave generation via difference frequency mixed in GaAs and Inp

The collinearly phase-matching condition of terahertz-wave generation via difference frequency mixed in GaAs and InP is theoretically studied. In collinear phase-matching,the optimum phase-matching wave bands of these two crystals are calculated. The optimum phase-matching wave bands in GaAs and InP are 0.95～1.38 mm and 0.7～0.96 mm respectively. The influence of the wavelength choice of the pump wave on the coherent length in THz-wave tuning is also discussed. The influence of the temperature alteration on the phase-matching and the temperature tuning properties in GaAs crystal are calculated and analyzed. It can serve for the following experiments as a theoretical evidence and a reference as well.     

THE STUDY OF LATTICE MATCH IN GaInAsP/InP HETEROJUNCTION LPE LAYERS

The effects of the growth conditions of two-phase solution liquid phase epitaxy(LPE)(i.e.growth temperature,cooling rates and solution composition)on lattice mismatch and band-gapwavelength in GaInAsP/InP heterojunction LPE layers have been investigated by X-ray double-crystal diffractometry and double-beam spectrophotometry.The stress in the grown interface freeof misfit dislocations and lattice mismatch at growth temperature have been calculated.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

SDN-Based Data Offioading for 5G Mobile Networks

The rapid growth of 3G/4G enabled devices such as smartphones and tablets in large numbers has created increased demand formobile data services.Wi-Fi offloading helps satisfy the requirements of data-rich applications and terminals with improved multi-media.Wi-Fi is an essential approach to alleviating mobile data traffic load on a cellular network because it provides extra capaci-ty and improves overall performance.In this paper,we propose an integrated LTE/Wi-Fi architecture with software-defined net-working(SDN)abstraction in mobile backhaul and enhanced components that facilitate the move towards next-generation 5G mo-bile networks.Our proposed architecture enables programmable offloading policies that take into account real-time network condi-tions as well as the status of devices and applications.This mechanism improves overall network performance by deriving real-time policies and steering traffic between cellular and Wi-Fi networks more efficiently.     

应力和电阻率可控的适用于高品质因子MEMS器件的原位掺硼LPCVD多晶硅薄膜

The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition （LPCVD） are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600-800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems （MEMS） devices, especially in high resonance frequency （high-f） and high quality factor （high-Q） MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2-5 mΩ·cm. These reported approaches avoid the high temperature annealing process （〉 1000 ℃）, and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.     

应用于低中频和零中频DVB调谐器中8阶信道滤波器设计

An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves -52 dB and the out-band IM3 achieves -55 dB with -11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18μm CMOS process, consumes 4 mA current with 1.8 V power supply.     

Large-signal characterizations of DDR IMPATT devices based on group Ⅲ-Ⅴ semiconductors at millimeter-wave and terahertz frequencies

Large-signal （L-S） characterizations of double-drift region （DDR） impact avalanche transit time （IM- PATT） devices based on group III-V semiconductors such as wurtzite （Wz） GaN, GaAs and InP have been carried out at both millimeter-wave （mm-wave） and terahertz （THz） frequency bands. A L-S simulation technique based on a non-sinusoidal voltage excitation （NSVE） model developed by the authors has been used to obtain the high frequency properties of the above mentioned devices. The effect of band-to-band tunneling on the L-S properties of the device at different mm-wave and THz frequencies are also investigated. Similar studies are also carried out for DDR IMPATTs based on the most popular semiconductor material, i.e. Si, for the sake of comparison. A compara- tive study of the devices based on conventional semiconductor materials （i.e. GaAs, InP and Si） with those based on Wz-GaN shows significantly better performance capabilities of the latter at both mm-wave and THz frequencies.     

Survivable Virtual Network Mapping Using Optimal Backup Topology in Virtualized SDN

Software-Defined Network architecture offers network virtualization through a hypervisor plane to share the same physical substrate among multiple virtual networks. However, for this hypervisor plane, how to map a virtual network to the physical substrate while guaranteeing the survivability in the event of failures, is extremely important. In this paper, we present an efficient virtual network mapping approach using optimal backup topology to survive a single link failure with less resource consumption. Firstly, according to whether the path splitting is supported by virtual networks, we propose the OBT-I and OBT-II algorithms respectively to generate an optimal backup topology which minimizes the total amount of bandwidth constraints. Secondly, we propose a Virtual Network Mapping algorithm with coordinated Primary and Backup Topology （VNM-PBT） to make the best of the substrate network resource. The simulation experiments show that our proposed approach can reduce the average resource consumption and execution time cost, while improving the request acceptance ratio of VNs.     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

Distributed Power Control for Energy Conservation in Hybrid Cellular Network with Device-to-Device Communication

Device-to-Device （D2D） com- munication has been proposed as a promising implementation of green communication to benefit the existed cellular network. In order to limit cross-tier interference while explore the gain of short-range communication, we devise a series of distributed power control （DPC） schemes for energy conservation （EC） and enhancement of radio resource utilization in the hybrid system. Firstly, a constrained opportunistic power control model is built up to take advantage of the interference avoidance methodology in the presence of service requirement and power constraint. Then, biasing scheme and admission control are added to evade ineffective power consumption and maintain the feasibility of the system. Upon feasibility, a non-cooperative game is further formulated to exploit the profit in EC with minor influence on spectral efficiency （SE）. The convergence of the DPC schemes is validated and their performance is confirmed via simulation results.     

具有频率调谐的GNSS接收机双模复数滤波器

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18μm CMOS process.This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz.A fully differential OTA with source degeneration is used to provide sufficient linearity.Furthermore,a ring CCO based frequency tuning scheme is proposed to reduce frequency variation.The measured results show that in narrow-band mode the image rejection ratio（IMRR）is 35 dB,the filter dissipates 0.8 mA from the 1.8 V power supply,and the out-of-band rejection is 50 dB at 6 MHz offset.In wide-band mode,IMRR is 28 dB and the filter dissipates 3.2 mA.The frequency tuning error is less than±2%.