Matrix unit cell scheduler (MUCS) for input-buffered ATM switches

This paper presents a novel matrix unit cell scheduler (MUCS) for input-buffered asynchronous transfer mode (ATM) switches. The MUCS concept originates from a heuristic strategy that leads to an optimal solution for cell scheduling. Numerical analysis indicates that input-buffered ATM switches scheduled by MUCS can utilize nearly 100% of the available link bandwidth. A transistor-level MUCS circuit has been designed and verified using HSPICE. The circuit features a regular structure, minimal interconnects, and a low transistor count. HSPICE simulation indicates that using 2-μm CMOS technology, the MUCS circuit can operate at clock frequency of 100 MHz     

Guaranteeing delay in ATM switches by using output port QoScontrollers

An ATM quality of service (QoS) controller which combines per-connection buffer management with a table-driven cell scheduler to achieve a broad range of QoS behaviours is proposed. The results show that as a constant bit rate (CBR) or variable bit rate (VBR) virtual connection spans across multiple switches, the QoS controller can firmly guarantee that the connection does not become burstier     

Survey of switching techniques in high-speed networks and their performance

One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (asynchronous transfer mode). ATM can be characterized by very high speed transmission links and simple, hard-wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks. A number of designs have been proposed for implementing ATM switches. Although many differences exist among the proposals, the vast majority of them are based on self-routeing multistage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routeing capability and suitability for VLSI implementation. Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques have also been proposed to improve the performance of blocking and non-blocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues.     

The single-queue switch: a building block for switches withprogrammable scheduling

We introduce a new approach to ATM switching. We propose an ATM switch architecture which uses only a single shift-register-type buffering element to store and queue cells, and within the same (physical) queue, switches the cells by organizing them in logical queues destined for different output lines. The buffer is also a sequencer which allows flexible ordering of the cells in each logical queue to achieve any appropriate scheduling algorithm. This switch is proposed for use as the building block of large-stale multistage ATM switches because of low hardware complexity and flexibility in providing (per-VC) scheduling among the cells. The switch can also be used as scheduler/controller for RAM-based switches. The single-queue switch implements output queueing and performs full buffer sharing. The hardware complexity is low. The number of input and output lines can vary independently without affecting the switch core. The size of the buffering space can be increased simply by cascading the buffering elements     

High performance real-time neural scheduler for ATM switches

Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, we formulate and evaluate a new neural scheduler with bounded response time     

Realization of large capacity ATM switches

Large-capacity ATM switches, with switching capacity in excess of 40 Gb/s or 100 Gb/s, are becoming an essential part of network growth. To realize such switches requires technology know-how as well as implementation trade-off considerations. This article provides a system-level exploration of large-capacity ATM switches in terms of switch fabric scalability, cell buffer management, buffer design trade-off, call processing capabilities, and future trends in switch design     

A distributed scheduling architecture for scalable packet switches

The continuous growth in the demand for diversified quality-of-service (QoS) guarantees in broadband networks introduces new challenges in the design of packet switches that scale to large switching capacities. Packet scheduling is the most critical function involved in the provision of individual bandwidth and delay guarantees to the switched flows. Most of the scheduling techniques proposed so far assume the presence in the switch of a single contention point, residing in front of the outgoing links. Such an assumption is not consistent with the highly distributed nature of many popular architectures for scalable switches, which typically have multiple contention points, located in both ingress and egress port cards, as well as in the switching fabric. We define a distributed multilayered scheduler (DMS) to provide differentiated QoS guarantees to individual end-to-end flows in packet switches with multiple contention points. Our scheduling architecture is simple to implement, since it keeps per-flow scheduling confined within the port cards, and is suitable to support guaranteed and best-effort traffic in a wide range of QoS frameworks in both IP and ATM networks     

A Shared Buffer Memory ATM Access Switch

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Switching using parallel input-output queued switches with no speedup

We propose an efficient parallel switching architecture that requires no speedup and guarantees bounded delay. Our architecture consists of k input-output-queued switches with first-in-first-out queues, operating at the line speed in parallel under the control of a single scheduler, with k being independent of the number N of inputs and outputs. Arriving traffic is demultiplexed (spread) over the k identical switches, switched to the correct output, and multiplexed (combined) before departing from the parallel switch. We show that by using an appropriate demultiplexing strategy at the inputs and by applying the same matching at each of the k parallel switches during each cell slot, our scheme guarantees a way for cells of a flow to be read in order from the output queues of the switches, thus, eliminating the need for cell resequencing. Further, by allowing the scheduler to examine the state of only the first of the k parallel switches, our scheme also reduces considerably the amount of state information required by the scheduler. The switching algorithms that we develop are based on existing practical switching algorithms for input-queued switches, and have an additional communication complexity that is optimal up to a constant factor.     

A Distributed Fair Queueing (DFQ) Architecture for Wireless ATM Local Access Networks

The application of Asynchronous Transfer Mode (ATM) to a Wireless Local Area Network (WLAN) environment is an undertaking that poses many problems not encountered in either wireline ATM or data-only WLAN. Wireline ATM networks do not have to transmit over multiple-access, unreliable transmission media while data-only WLANs do not have to satisfy heterogeneous Quality of Service (QoS) contracts for multimedia services. To address this issue, we propose in this paper a DFQ-based WLAN architecture, designed as a centrally controlled network where a complex base station polls simpler mobile terminals for channel access.DFQ is an implementation of Fair Queueing (FQ) algorithm to schedule the access to the transmission channel among the mobile terminals. The implementation of DFQ introduces new design challenges, mainly in the packet scheduler. A DFQ scheduler is designed to allow fast and efficient processing of scheduling data. The DFQ algorithm is introduced and simulated for delay-sensitive connections, and the hardware implementation of the packet scheduler is discussed.The Centre for Wireless Communications is a national R&D Centre funded by the Singapore National Science and Technology Board     

一种ATM交换结构性能分析方法

本文给出了ＡＴＭ交换结构性能分析的有效数学方法，通过分析几种业务流情况下不同缓冲方式ＡＴＭ交换结构的信元丢失率和时延特性，证明了该方法的正确性和有效性。     

Warren: a low-cost ATM home area network

This article introduces the concept of the ATM Warren. The Warren is an arbitrary mesh subnetwork of very simple ATM switches and end stations connected to the wide-area B-ISDN at one or more points. The Warren differs from other ATM networks in that both switches and end stations are designed to be implemented entirely in hardware with all control software banished to external computers     

Wireless ATM: Performance Evaluation of a DSA++ MAC Protocol with Fast Collision Resolution by a Probing Algorithm

In general, the users of wireless ATM terminalsrequest the same functionality and quality of service asusers of wired terminals. These user requirements can betransformed into the demand for building an ATM multiplexer around the air interfacewhich is characterized by a radio channel inside. Themain difference between this virtual ATM multiplexeraround the air interface and a fixed ATM multiplexer is the distribution of the multiplexingfunction between wireless terminals and the basestation. For the uplink this requires a frequentnotification of the ATM cell scheduler in the basestation about the status of the incoming buffers inside thewireless terminals. This paper focuses on differentmethods for transmitting capacity request messages (alsodesignated as reservation request) over theuplink.     

Module Matching Schemes for Input-Queued Clos-Network Packet Switches

Current schemes for configuration of input-queued three-stage Clos-network (IQC) switches involve port matching and path routing assignment, in that order. The implementation of a scheduler capable of matching thousands of ports in large-size switches is complex. To decrease the scheduler complexity for such switches (e.g., 1024 ports or more), we propose a configuration scheme for IQC switches that hierarchizes the matching process. In a practical scenario our scheme performs routing first and port matching thereafter. This approach reduces the scheduler size and the configuration complexity of IQC switches. We show that the switching performance of the proposed approach using weight-based and weightless selection schemes is high under uniform and nonuniform traffic     

An iterative cell scheduling algorithm for ATM input-queued switchwith service class priority

An iterative cell scheduling algorithm for asynchronous transfer mode (ATM) input-queued switch with service class priority is proposed in this paper. At inputs of the switch the VC's or VP's are discriminated into classes of services and in each class an iterative round robin matching scheduler is provided. A performance analysis is carried out by simulation and the results show a very promising ATM switch for the proposed algorithm     

Polling- and contention-based schemes for TDMA-TDD access towireless ATM networks

The design of an efficient MAC protocol is of paramount interest for the definition of a wireless ATM (WATM) access. In the case of TDMA-TDD WATM access, the current trend in the standardization bodies is to adopt frames of fixed duration, whose slots are shared among uplink and downlink connections under the control of a MAC scheduler located in the base station. In this paper, we first compare polling and contention techniques, in order to identify the best access scheme to serve ATM connections. Then, since the knowledge of the queue status of the portable terminals can be used by the centralized scheduler to increase the efficiency of the slot assignment procedure, we propose different algorithms to code the buffer occupancy status. Moreover, we compare their performance by considering two different scenarios; the first loaded with ON-OFF sources served by nrt-VBR ATM connections, and the second with TCP/IP sources served by UBR ATM connections. The results show the superiority of the contention access and the advantages of the buffer status notification for the scheduler at the base station     

Parallel contention resolution control for input queueing ATM switches

Input queueing ATM switches requiring fast contentional resolution control have been negatively affected by long turn-around time (TAT) due to the distance between an input port controller and a centralised contention controller. A parallel contention resolution control for input queueing switches is presented. The proposed control allows a TAT of more than one cell slot, resulting in the potential development of a centralised contention controller for an ATM switch with an aggregate capacity of 1 Tbit/s.<>     

ATM市场需求及典型产品

目前，ＡＴＭ已由技术驱动转为市场驱动和业务驱动。本文分析讨论了ＡＴＭ技术的市场及业务需求，对ＡＴＭ的相关产品进行了简单分类，并简要介绍和比较了几种典型的ＡＴＭ交换机的性能和各自采用的设计方案。     

Performance issues in public ABR service

The available bit rate (ABR) service attracted much attention during the negotiations leading to Traffic Management Specification Version 4.0, finalized by the ATM Forum. In thr ABR service, feedback flow control of the source rate is provided in response to the changing asynchronous transfer mode (ATM)-layer transfer characteristics. The reference behavior of the source end system, the destination end system, and the switch, as detailed in the specification, allows cooperative control among these systems. The performance of the public ABR service is discussed in connection with the evolution of ATM switches. Public networks with first-generation switches provide an ABR service with a limited peak cell rate (PCR), while those with second-generation switches can provide an ABR service with any PCR. In such networks, TCP-over-ABR works well. Point-to-multipoint ABR will be provided in advanced switches. A method is proposed for maintaining the throughput of point-to-multipoint ABR when the number of leaves is increased     

A new fast cell resequence mechanism for multipath ATM switches

A new cell resequence mechanism is proposed to restore the cell sequence in multipath ATM switches. Since the proposed mechanism uses per-VC logical queues which store only the cells belonging to the same VC, the mechanism can reduce processing time compared to conventional resequence mechanisms. The mechanism also has no limitation on the peak rate of the VCs and needs no arbitration function to select an output cell. The mechanism can be implemented using a RAM buffer, a content addressable memory/random access memory (CAM/RAM) table, a controller, etc