深亚微米SOI栅控混合管(GCHT)的准二维电流解析模型

提出了深亚微米SOIGCHT电流模型.不同于普通MOSFET短沟模型的处理,计及受栅电压及基极电压同时控制的可动电荷的影响,采用准二维分析及抛物线近似,求出沟道长度及漏端电压对源端表面势的影响,较好地反映了电荷共享效应及DIBL效应,并定量计算出与漏电压和栅电压同时相关的动态阈值电压漂移量.模型中同时考虑了速度饱和效应、迁移率下降效应和沟道长度调制效应等.该模型具有清晰的物理意义,从理论上解释了GCHT具有较小的短沟效应及较高的阈值电压稳定性等物理现象.模型计算结果与数值模拟及实验结果吻合良好,较好地描述了短沟GCHT的物理特性.     

Bulk charge effects in VLSI MOSFET's

An analysis of the relative magnitudes of the bulk charge for three MOSFET structures suitable for VLSI devices, such as NMOS (normal), VMOS (V slot) and UMOS (U slot), is carried out. It is shown that even for the same channel design (i.e. channel length, doping, source/drain junction depth, and oxide thickness), the amount of bulk charge and hence the threshold voltage can be significantly different for the three structures. This effect becomes more important with decreasing channel length, and increasing source to substrate bias. Further, for a given channel length, the bulk charge and hence the threshold voltage of an NMOS decreases with increasing source/drain junction depth. However, for the VMOS and UMOS structures, the bulk charge as well as the threshold voltage do not depend on the junction depth of the source/drain diffusion. An expression is also derived for the bulk charge of UMOS transistors valid for both short and long channels.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

An analytical drain current model for submicrometer and deepsubmicrometer MOSFET's

In this paper, we present a new, analytical, and physics-based drain current model for both submicrometer and deep submicrometer MOSFET's. The model was developed by starting from a two-dimensional (2D) Poisson equation and using the energy balance equation. Using the present model, we can clearly see that the drain current increases with decreasing channel length due to a larger average channel mobility at shorter channel length. The formulas for the saturation drain voltage and the drain current can be reduced to their corresponding well-known formulas in the submicrometer range. The accuracy of the presented model has been verified with the experimental data of metal-oxide-semiconductor (MOS) devices with various geometries     

A compact pre- and post-stress I-V model for submicrometerburied-channel pMOSFETs

In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.     

应变PMOS二维阈值电压解析模型

利用准二维方法求解二维泊松方程,建立了锗硅源漏单轴应变PMOS阈值电压的二维解析模型,理论计算结果和实验报道的结果能很好吻合。研究了不同沟道长度和漏压情况下的沟道表面势,分析了沟道长度、漏压及锗硅源漏中锗摩尔组分等参数对阈值电压的影响。利用TCAD工具进行仿真模拟,结果表明,沟道长度和漏压是单轴应变PMOS阈值电压漂移的主要影响因素,而锗摩尔组分在一定成分范围内影响较小。     

A geometrical model of the threshold voltage of short and narrow channel MOSFETs

A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program.     

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

New short-channel n-MOSFET current-voltage model in stronginversion and unified parameter extraction method

A semiempirical strong inversion current-voltage (I-V) model for submicrometer n-channel MOSFETs which is suitable for circuit simulation and rapid process characterization is proposed. The model is based on a more accurate velocity-field relationship in the linear region and finite drain conductance due to the channel length modulation effect in the saturation region. The parameter extraction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. These results are used in order to systematically extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate length and characteristic length for channel length modulation, and short-channel effects. The values agree well with other independent measurements. The results of experimental studies of wide n-MOSFETs with nominal gate length of 0.8, 1.0, and 1.2 μm fabricated by an n-well CMOS process are reported. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results     

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V_PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V_BD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V_PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V_BD, however, decreases as the channel length, oxide thickness and diffusion depth decrease.Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.     

The characterization of hot carrier damage in p-channel transistors

Damage in surface channel p-MOS transistors arising from hot-carrier stress is examined using a recently proposed lifetime extraction method. It is shown that the p-MOS behavior with respect to hot-carrier stress runs counter to that of n-MOS transistors in many respects and has to be considered separately. Not only are the well-known post-stress gains in drive current obtained for p-MOS transistors, but also the measurement of the I-V characteristics with the stress damage at the source and drain ends shows effects opposite to those of n-MOS devices. This is attributed to coulombic screening by the channel charge. Stressing transistors in inverter-like and pass-transistor-like modes are also discussed, and it is found that p-MOS transistors are much more sensitive to pass-transistor-like damage than n-channel devices, due to increased channel length shortening in the pass transistor mode. It is shown that whereas at long gate lengths (>0.5 μm) the degradation is limited to drain current changes, at shorter channel lengths (<0.5 μm), significant threshold voltage shifts arise     

A simple approach for accurately modeling the threshold voltage of short-channel mosts

We present a theory which models short-channel effects in MOS transistors (MOST). Our approach accounts for the effects of the source and drain depletion regions on the energy band configuration and the effective depletion layer charge under the channel. We derive an equation for low drain bias threshold voltage which accurately predicts the measured threshold on devices ranging in size from very small (1.5 μm) to very large (100 μm) effective channel lengths. The equation reliably predicts the phenomenon of decreasing threshold voltage and body effect observed experimentally from devices of decreasing channel length. The equation is valid for any bulk silicon MOS technology provided that the substrate doping is approximately uniform (i.e. ion-implantation has not been used to adjust the threshold). Our approach can be applied directly to the modeling of the short-channel drain to source current. This application of the theory will be presented in a later paper.     

Threshold voltage theory for a short-channel MOSFET using a surface-potential distribution model

A detailed expression of the threshold voltage for a short-channel MOSFET is derived from a model of surface-potential distribution under the gate using a relationship of surface-channel charge neutrality. The theory is compared with the measured threshold voltages. The theoretical curves for threshold voltage over a wide range of drain and backgate voltage are in good agreement with experimental results. It is shown for a MOSFET having a channel length less than 2 μm that the body-bias constant increases as the drain voltage increases. The theory also predicts that the increase in backgate voltage leads to the reduction in short-channel effect for the shorter-channel case.     

A model for anomalous short-channel behavior in submicron MOSFETs

Experimental data and simulation results for submicron MOSFETs are reported and used to support a physical explanation for two important anomalies in the dependence of device threshold voltage on channel length. They are the widely observed increase in threshold voltage with decreasing channel length (roll-up), and the more recent observation that the ultimate threshold voltage decrease (roll-off) occurs at a rate which is far in excess of that which can be explained with conventional models of laterally uniform channel doping. A model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed. This lateral redistribution is caused by crystal defects formed during post-source/drain-implant anneal. The resulting profile consists of an enhancement of background doping adjacent to the junction edge, bounded by a depression of the doping farther into the channel     

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.