1-Gb/s 80-dB/spl Omega/ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-/spl mu/m standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dB/spl Omega/ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-/spl mu/A average input noise current, -17-dBm sensitivity for 10/sup -12/ bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.     

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBTlimiting amplifier

A limiting amplifier IC implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology for low-cost 10-Gb/s applications is described. The IC employs 20 dB gain limiting cells, input overload protection, split analog-digital grounds, and on-chip isolation interface with transmission lines. A gain enhancement technique has been developed for a parallel-feedback limiting cell. The limiting amplifier sensitivity is less than 3.5 mV_pp at BER=10^-9 with 2-V_pp maximum input (55-dB dynamic range). The total gain is over 60 dB, and S₂₁ bandwidth exceeds 15 GHz at 10-mV_pp input. Parameters S₁₁ and S₂₂ are better than -10 dB in the 10-GHz frequency range. The AM to PM conversion is less than 5 ps across input dynamic range. The output differential voltage can be set from 0.2 to 2 V_pp with IC power dissipation from 250 mW to 1.1 W. The chip area is 1.2×2.6 mm². A 10-Gb/s optical receiver, built with the packaged limiting amplifier, demonstrated -19.6-dBm sensitivity. The IC can be used in 10-Gb/s fiber-optic receivers requiring high sensitivity and wide input dynamic range     

An auto-gain control transimpedance amplifier with low noise andwide input dynamic range for 10-Gb/s optical communication systems

This paper describes a 10-Gb/s transimpedance amplifier (TIA), fabricated in a 0.1-μm-p-HEMT technology. To improve the optical overload characteristics, an automatic gain control (AGC) circuit is included. The measured results show excellent performance, transimpedance of 63.3 dBΩ (1.46 kΩ), bandwidth of 8.0 GHz, and equivalent input noise current density of 6.5 pA/rtHz. When the bit error rate is 10^-9, the minimum sensitivity and the optical overload are -21.2 dBm, +4.3 dBm, respectively, using a 0.8 A/W pin photodiode (PD). The power dissipation is about 0.5 W from a single -5-V supply. The die area is 1.3×1.6 mm²     

Wide dynamic range parallel feedback transimpedance amplifier for 10 Gb/s optical links

This paper presents the design and implementation of a new wide dynamic range parallel feedback (PF) transimpedance amplifier (TIA) for 10 Gb/s optical links. The wide dynamic range is attributed to the novel TIA architecture employing both shunt-shunt and shunt-series feedback networks. The outstanding features of the TIA are wide dynamic range, high gain, low power consumption and design simplicity. A prototype implemented in a 0.5 μm SiGe BiCMOS technology and operating at −3.3 V power supply features an 18.4 dBm dynamic range with a BER less than 10⁻¹², an optical sensitivity of −16 dBm, optical overload of +2.4 dBm, a bandwidth of 8.27 GHz, a gain of 950 Ω and a power consumption of 189 mW. The new parallel feedback architecture offers improved overload and noise performance when compared to previously reported, state of the art, single feedback TIA designs and meets all the 10 Gigabit Ethernet and short-reach OC-192 SONET specifications. Ricardo Andres Aroca received the B.S. (Hons) degree in electrical engineering from the University of Windsor, Canada, and the M.S. degree from the University of Toronto, Canada, in 2001 and 2004, respectively. In 2000 he spent two 4 month internships with Nortel Networks in the Microelectronics Department. Mr. Aroca received the Natural Sciences and Engineering Research Counsel of Canada (NSERC) Postgraduate Scholarship award in 2002. He is currently working toward the Ph.D. degree at the University of Toronto where his research interests lie in the area of high-frequency integrated circuits for wireless and wireline communication systems. C. Andre T. Salama received the B.A.Sc. (Hons.) M.A.Sc. and Ph. D. degrees, all in Electrical Engineering, from the University of British Columbia in 1961, 1962 and 1966 respectively. From 1962 to 1963 he served as a Research Assistant at the University of California, Berkeley. From 1966 to 1967 he was employed at Bell Northern Research, Ottawa, as a Member of Scientific Staff working in the area of integrated circuit design. Since 1967 he has been on the staff of the Department of Electrical and Computer Engineering, University of Toronto where he held the J.M. Ham Chair in Microelectronics from 1987 to 1997. In 1992, he was appointed to his present position of University Professor for scholarly achievements and preeminence in the field of microelectronics. In 1989-90, he was awarded the ITAC/NSERC Research Fellowship in information technology. In 1994, he was awarded the Canada Council I.W. Killam Memorial Prize in Engineering for outstanding career contributions to the field of microelectronics. In 2000, he received the IEEE Millenium Medal. In 2003, he received the Outstanding Lifetime Achievement Award from the Canadian Semiconductor Technology Conference for seminal and outstanding contributions to semiconductor device research and promotion of Canadian University research in microelectronics. In 2004, he received the NSERC Lifetime Achievement Award of Research Excellence for outstanding and sustained contributions to the field of microelectronics and the Networks of Centres of Excellence (NCE) Recognition Award for research excellence and outstanding leadership.He was associate editor of the IEEE Transactions on Circuits and Systems in 1986–88 and a member of the International Electron Devices Meeting (IEDM) Technical Program Committeein 1980–82, 1987–89 and 1996–98. He was the chair of the Solid State Devices Subcommittee for IEDM in 1998 and was a member of the editorial board of Solid State Electronics from 1984 to 2002. He is presently a member of the editorial board of the Analog IC and Signal Processing Journal and the Technical Program Committee of the International Symposium on Power Semiconductor Devices and ICs (ISPSD) and the Technical ProgramCommittee of the International Symposium on Low Power Electronics and Design (ISLPED). He chaired the technical program committee of ISPSD in 1996 and was the general chair for the conference in 1999.Dr. Salama is the Scientific Director of Micronet, a network of centres of excellence focussing on microelectronics research and funded by the Canadian Government and Industry. He has published extensively in technical journals, is the holder of eleven patents and has served as a consultant to the semiconductor industry in Canada and the U.S. His research interests include the design and fabrication of semiconductor devices and integrated circuits with emphasis on deep submicron devices as well as circuits and systems for high speed, low power signal processing applications. Dr. Salama is a Fellow of the Institute of Electrical and Electronics Engineers, a Fellow of the Royal Society of Canada, a Fellow of the Canadian Academy of Engineering, a member of the Association of Professional Engineers of Ontario, the Electrochemical Society and the Innovation Management Association of Canada.     

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.     

A 43-Gb/s full-rate clock transmitter in 0.18-/spl mu/m SiGe BiCMOS technology

A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120 GHz f/sub T/ and 100 GHz f/sub max/ HBTs. It consists of a 4:1 multiplexer, a clock multiplier unit, and a frequency lock detector. The IC features clock jitter generation of 260 fs rms and dissipates 2.3 W from a -3.6-V supply voltage. Measurement results are compared to a previously reported half-rate clock transmitter designed using the same technology.     

10-Gb/s modulator drivers with local feedback networks

A novel intrinsic collector-base capacitance (C/sub CB/) feedback network (ICBCFN) was incorporated into the conventional cascode and series-connected voltage balancing (SCVB) circuit configurations to implement 10-Gb/s modulator drivers. The drivers fabricated in 0.35-/spl mu/m SiGe BiCMOS process could generate 9 V/sub PP/ differential output swings with rise/fall time of less than 29 ps. Also, the ICBCFN was modified as an intrinsic drain-gate capacitance feedback network (IDGCFN) to implement drivers with differential output swing of 8 V/sub PP/ in 0.18-/spl mu/m CMOS process. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than that of the currently reported silicon-based drivers.     

20 mW 1.25 Gbit/s CMOS transimpedance amplifier with 30 dB dynamic range

A 1.25 Gbit/s transimpedance amplifier using a novel photodiode capacitance cancellation technique has been demonstrated in 0.35 mum CMOS technology. The transimpedance amplifier achieved a transimpedance gain of 17.1 kOmega as well as a wide dynamic range from +1 to -29 dBm while consuming only 20 mW from a 3 V supply     

Resonator-based multi-stage /spl Sigma//spl Delta/ modulator for wideband applications with improved dynamic range

A new design methodology for wideband, multi-stage, multi-bit /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) with improved dynamic range, is presented. The key to improving dynamic range is to have the first stage oscillated, then the coarse quantisation noise vanishes and hence circuit non-linearities do not cause a leakage quantisation noise problem. Based on the proposed methodology, a fourth-order four-bit /spl Sigma//spl Delta/M can achieve the dynamic range of 80 dB at the OSR of 8 without using additional calibration techniques.     

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to keep the design compact and power efficient. The transmitter includes a differential to single-ended modulator and a two-stage power amplifier (PA). The receiver includes a low-noise amplifier (LNA), pre-amplifiers, envelope detectors (ED), a variable gain amplifier (VGA), and a comparator. The chip is fabricated in 180-nm SiGe BiCMOS technology. With power-efficient transceivers and low-cost high-performance antennas, the implemented inter-chip link achieves bit-error rate (BER) around 10^-8 for 6 Gb/s over a distance of 2 cm. The signal-to-noise ratio (SNR) of the recovered signal is about 24 dB with 18 ps of rms jitter. The transmitter and receiver consume 57 mW and 60 mW, respectively, including buffers. The bit energy efficiency excluding test buffers is 17 pJ/bit. The presented work shows the feasibility of a low power high data rate wireless inter-chip data link and wireless heterogeneous multi-chip networks.     

A high dynamic range current-mode amplifier for computed tomography

In this paper, we show a high dynamic range current-mode detector for computed tomography application. A regulated current mirror structure has been implemented at pixel level that provides with 17 bits dynamic range and a noise floor below 3 pARMS. Nonlinearity is kept below 2% and signal bandwidth is higher than 10 kHz. A test structure with 4/spl times/4 pixel array is presented is this paper. Both photodiode and current mode amplifier have been integrated into the same CMOS standard process.     

A high dynamic range ultralow-current-mode amplifier with pico-ampere sensitivity for biosensor applications

A novel ultralow-current-mode amplifier (ULCA) serving for on-chip biosensor signal pre-amplification in the integrated biosensing system (IBS) has been presented and verified in SMIC 0.18 μm CMOS technology by elaborately considering gain, bandwidth, noise, offset, and mismatch. The proposed ULCA solved the noise, bandwidth, and current headroom dilemma in the reported works, and can completely satisfy the specifications of IBS. It provides a current gain of 20 dB, 3 dB bandwidth of 7.03 kHz and input dynamic range of 20 bit, with only 1 nA of DC quiescent current, while the input offset current and noise current are less than 16.0 pA and 4.67 pArms, respectively.     

A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver

A transimpedance amplifier packaged with an InP p-i-n photodiode has been demonstrated for 10-Gb/s SONET receiver. The shunt feedback transimpedance amplifier is fabricated in 0.25-μm modular Si BiCMOS technology. The transimpedance of 55 dBΩ is achieved at a bandwidth of 9 GHz by applying shunt peaking and filter termination at the input. The optical sensitivity of -17 dBm was measured at 10 Gb/s for a bit-error rate of 10^-12     

A fully integrated 5.3-GHz 2.4-V 0.3-W SiGe bipolar power amplifier with 50-/spl Omega/ output

A radio frequency power amplifier for 4.8-5.7 GHz has been realized in a 0.35-/spl mu/m SiGe bipolar technology. The balanced two-stage push-pull power amplifier uses two on-chip transformers as input-balun and for interstage matching. Further, it uses three coils for the integrated LC-output balun and the RF choke. Thus, the power amplifier does not require any external components. At 1.0-V, 1.5-V, and 2.4-V supply voltages, output powers of 17.7 dBm, 21.6 dBm, and 25 dBm are achieved at 5.3 GHz. The respective power-added efficiencies (PAE) are 15%, 22%, and 24%. The small-signal gain is 26 dB. The output 1-dB compression point at 2.4 V is 22 dBm with a PAE of 14%.     

A 0.18 μm CMOS transimpedance amplifier with 26 dB dynamic range at 2.5 Gb/s

A new transimpedance amplifier (TIA) for 2.5 Gb/s optical communications fabricated in a standard 0.18 μm CMOS process is presented. The proposed TIA is based on a conventional structure with an inverting voltage amplifier and a feedback resistor, but incorporates a new technique to enhance the input dynamic range and to prevent the TIA from saturation at high input currents. According to electrical characterization the receiver shows an optical sensitivity of −26 dB m for a BER=10⁻¹², assuming a responsivity of 1 A/W, and an optical power dynamic range above 26 dB. The power consumption of the core is only 10.6 mW at a single supply voltage of 1.8 V.     

10 Gb/s 带有直流漂移校正的dB线性、无电感宽带可变增益放大器

本文介绍了一款带有直流漂移校正的dB线性、无电感宽带可变增益放大器。该可变增益放大器包含一个可变增益模块,一个带有共模电压调整的直流漂移校正模块,以及一个带宽拓展模块。为了放大器带宽同时节约芯片面积,本设计中带宽拓展模块采用了一种无电感设计的有源反馈技术,通过该模块在高频增益过冲来补偿可变增益模块和直流漂移校正模块在高频处的增益下降,从而达到拓展带宽、提高增益的效果。该可变增益放大器采用0.13mm SiGe BiCMOS工艺。测试结果表明,该款放大器3 dB带宽达到7.5 GHz,可变增益范围为40 dB (-10 dB-30 dB)。在10 Gb/s伪随机测试码输入的情况下,测试输出信号峰峰抖动小于30 ps_pp,功耗为50 mW。由于无电感设计,该芯片的面积仅为0.53*0.27 mm₂。     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

A DC-coupled wide dynamic range AGC amplifier IC for 560-Mbit/s optical transmission

A wide-band high-gain AGC amplifier stabilizing the output dc level against a broad gain variation is proposed and monolithically integrated using high-speed 1-μm Si-bipolar IC technology. The fabricated IC exhibits a maximum gain of 39 dB, gain dynamic range of 44 dB, bandwidth of 800 MHz, and output dc-level fluctuation of 8 mV, and realizes wide dynamic range and direct dc-coupling of the multistage AGC amplifier. Also, in order to examine the feasibility of the fabricated IC, a 1.5-μm-wavelength optical transmission experiment was carried out using DFB-LD and InGaAs-APD. Measured minimum received optical power for an error rate of 10^-9is -40 dBm at 560 Mbit/s and -38 dBm at 1.12 Gbit/s. Optical dynamic range of 30 dB is also achieved by using the fabricated IC and APD.     

一种光接收机中的高增益宽动态范围跨阻放大器

As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.