Current mode single-input multi-output MOSFET-only filter

In this paper, a very simple topology of a current mode MOSFET-only filter with single-input and multi-output is proposed. It is very important to emphasize that it is possible to obtain five of the filter functions, namely low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) using the proposed topology without using external passive elements. The core circuit of the proposed filter employs only four MOS transistors; therefore, it occupies very small chip area. It is also possible to adjust the filter gain with the biasing voltage. In addition, the circuit exhibits a very low input impedance and also high output impedances which make it possible for cascading. The MOSFET capacitances which determine the transfer functions are all grounded, so physical capacitances can be used instead of MOSFET parasitic capacitances to operate the filter at very low frequencies. Moreover, proposed filter structure has low supply voltage as 1 V in order to be applicable to low voltage operations. Detailed simulation results, including noise and Monte Carlo analysis, are provided using 0.18 µm TSMC technology parameters to verify the feasibility of the filter circuit.     

Arbitrary real-order cost functions for signals and systems

This work focuses on a new type of cost function based on fractional operators. To do so, the concept of definite integral is extended to arbitrary real-order. Some properties of this new fractional-order definite integral are studied and a fractional-order Barrow's rule is proposed. It is illustrated by an example (the design of an IIR filter) how this new kind of cost function can be a valuable tool in problems where optimal design methods are involved.     

A New CMOS Programmable Balanced Output Transconductor and Application to a Mixed Mode Universal Filter Suitable for VLSI

A new CMOS programmable balanced output transconductor (BOTA) is introduced. The BOTA is a useful block for continuous-time analog signal processing. A new CMOS realization based on MOS transistors operating in the saturation region is given. Application of the BOTA in realizing a mixed mode universal filter using six BOTAs and two grounded capacitors is also introduced. The filter's gain can be adjusted simply by varying the amplitude of a transconductance through its control voltage without affecting ₀ and Q of the filter. Also, the Q of the filter can be adjusted by a single transconductor independent of ₀. PSpice simulation results for the BOTA circuit and for the universal filter are also given.     

Ultra-low voltage fractional-order differentiator and integrator topologies: an application for handling noisy ECGs

Fractional-order differentiator and integrator topologies are introduced in this paper. They offer the benefits of resistorless realizations, electronic adjustment of their characteristics, and capability for operating in 0.5 V power supply voltage. These have been achieved through the employment of the concept of the Sinh-Domain filtering. The performance of the proposed blocks has been evaluated through the Analog Design Environment of the Cadence software, using MOS transistor models provided by the TSMC 180 nm process. As application example, the design of a Sinh-Domain chain for realizing the preprocessing of the Pan-Tomkins algorithm has been given, where the conventional differentiator has been substituted by a fractional-order differentiator.     

改进型跳耦结构电流镜滤波器

提出了一种利用电流镜积分器和微分器实现的改进型跳耦结构滤波器,讨论并比较了跳耦结构和改进型跳耦结构滤波器的设计方法,改进方法突破了单纯用电流镜积分器实现滤波器的局限,简化了椭圆函数滤波器的信号流图和电路结构;完成了MOS级的计算机仿真,仿真结果表明所提出的电路方案正确有效。     

Low Voltage Micropower Log-Domain Filters

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-m mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm² without the i/o pads     

New CMOS Fully‐Differential Transconductor and Application to a Fully‐Differential Gm‐C Filter

A new CMOS voltage‐controlled fully‐differential transconductor is presented. The basic structure of the proposed transconductor is based on a four‐MOS transistor cell operating in the triode or saturation region. It achieves a high linearity range of ± 1 V at a 1.5 V supply voltage. The proposed transconductor is used to realize a new fully‐differential Gm‐C low‐pass filter with a minimum number of transconductors and grounded capacitors. PSpice simulation results for the transconductor circuit and its filter application indicating the linearity range and verifying the analytical results using 0.35 μm technology are also given.     

Design of a tunable frequency CMOS fully differential fourth-order Chebyshev filter

A new fully differential amplifier and a fully differential R-MOSFET-C fourth-order Chebyshev active lowpass filter employing passive resistors and current-steering MOS transistors as variable resistors are proposed. The implementation relies on the tunability of current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the cutoff frequency of Chebyshev active filter can be realized accurately tunable. The amplifier is not only with voltage common-mode negative feedback (VCMFB), but also with current common-mode negative feedback (CCMFB), which will benefit for the stability of its DC operating point. A cutoff frequency of 138 kHz fourth-order Chebyshev lowpass filter was designed and fabricated using 3.3 V power supply and 0.35 μm CMOS technology. Chip test results demonstrate better than −68 dB THD with 70 kHz, 2.0V_pp signal, frequency turning range of more than 14,000 from 3 Hz to 420 kHz, chip area of 0.36 mm² and power consumption of 16 mW.     

Current-mode capacitorless integrators and differentiators for implementing emulators of fractional-order elements

Fractional-order capacitor and inductor emulator, implemented using current-mirrors as active elements and MOS transistors as capacitors, is introduced in this paper. Current-mirror integrators are used for performing the required current-mode integration/differentiation operation within the emulator stage. Also, a voltage-to-current converter, implemented using an Operational Transconductance Amplifier, is utilized for realizing the required interface of the input signal. Thus, the proposed emulator is simultaneously capacitorless and resistorless and offers the advantage of electronic tuning of the characteristics as well as of the type of the emulated fractional-order element. In addition, a modified version of the emulator that allows current excitation is proposed. The evaluation of the behavior of the proposed schemes has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.     

Efficient Design of Discrete Fractional-Order Differentiators Using Nelder–Mead Simplex Algorithm

Applications of fractional-order operators are growing rapidly in various branches of science and engineering as fractional-order calculus realistically represents the complex real-world phenomena in contrast to the integer-order calculus. This paper presents a novel method to design fractional-order differentiator (FOD) operators through optimization using Nelder–Mead simplex algorithm (NMSA). For direct discretization, Al-Alaoui operator has been used. The numerator and the denominator terms of the resulting transfer function are further expanded using binomial expansion to a required order. The coefficients of z-terms in the binomial expansions are used as the starting solutions for the NMSA, and optimization is performed for a minimum magnitude root-mean-square error between the ideal and the proposed operator magnitude responses. To demonstrate the performance of the proposed technique, six simulation examples for fractional orders of half, one-third, and one-fourth, each approximated to third and fifth orders, have been presented. Significantly improved magnitude responses have been obtained as compared to the published literature, thereby making the proposed method a promising candidate for the design of discrete FOD operators.     

On the practical realization of higher-order filters with fractional stepping

We propose the use of a compact integer-order transfer function approximation of the fractional-order Laplacian operator s^α to realize fractional-step filters. Lowpass and bandpass filters of orders (n+α) and 2(n+α), where n is an integer and 0<α<1, can, respectively, be designed. A 5th-order lowpass filter with fractional steps from 0.1 to 0.9 (i.e. 5.1→5.9) is given as an example with its characteristics compared to 5th- and 6th-order Butterworth filters. Spice simulations and experimental results are shown.     

Universal filters of arbitrary order and type employing square-root-domain technique

Novel Single Input Multiple Output (SIMO) and Multiple Input Single Output (MISO) universal filter topologies of arbitrary order and type are introduced in this paper. The proposed topologies have been realised by employing Square-Root Domain (SRD) technique. An offered benefit of the universal filter topologies is that only grounded capacitors are required for their implementations and the resonant frequency of the filters can be electronically controlled by an appropriate dc current. The proposed universal filters simultaneously offer all the five standard filtering functions i.e. Lowpass (LP), Highpass (HP) and Bandpass (BP), Bandstop (BS) and Allpass (AP) frequency responses. In addition, the SIMO topology is generic in the sense that it can yield four different stable filter configurations. Two design examples are provided in each configuration and the correct operation of the corresponding topologies has been evaluated through the PSPICE software with BSIM 0.35-µm CMOS process model parameters.     

Design of High Dynamic Range Fully Integratable Translinear Filters

This paper addresses the non-linear noise and dynamic-range properties of bipolar and MOS (both in weak and in strong inversion) translinear integrators, following a systematic top-down approach. Several design principles to achieve an optimal dynamic range are derived. A qualitative comparison of a bipolar or weak-inversion class-AB translinear integrator and the well-known linear g _m – C integrator reveals that the former is an interesting candidate, especially for low-voltage and/or low-power operation. As an example, a ±1.65-V bipolar translinear integrator is presented that makes dynamic-range optimization possible by adjusting just one bias current. Its application in an audio filter yields a 63-dB dynamic range and a virtual dynamic range of 76 dB, while the current consumption can be as low as 310 nA.     

Real-time programmable unit-element SC filter for LPC synthesis

The letter presents a novel programmable unit-element SC filter for LPC synthesis. The circuit is based on the theory of wave-flow networks. It has the advantage that for a programmable 10th-order unit-element SC filter only five programmable capacitor arrays are needed. The capacitive loading of every op amp is constant, thus simplifying the op amp design. The circuit is insensitive to stray capacitances which are commonly associated with integrated MOS capacitors and transistors. It also exhibits a low sensitivity to coefficient quantisations; hence, the circuit is well suited for integration in MOS technology.     

圆杆交指型滤波器的设计

介绍了圆杆交指型带通滤波器的设计原理和方法,根据交指滤波器的设计理论获得圆杆的自电容和互电容,利用计算机辅助设计工具进行数值计算,结合图表得到滤波器的最初尺寸。给出了一个中心频率为830 MHz圆杆交指滤波器的设计过程,利用HFSS软件仿真,提高了设计效率和精度,仿真结果和理论结果吻合良好,证明了设计方法的可行性。     

A Modified Particle Swarm Optimizer and its Application to the Design of Microwave Filters

In this paper, a modified particle swarm optimization (PSO) algorithm is presented and its applicability is shown for the design of specific microwave filter as a case study of microwave components. In the proposed modified PSO algorithm, particles in the swarm are divided to form multiple sub-swarms. The social component of PSO’s velocity update equation is modified to include the effects of multiple sub-swarms. Five benchmark functions have been considered for testing the proposed algorithm. The approach has been tested for two basic modifications of PSO namely PSO with inertia weight (IW) and PSO with constriction factor method (CFM). The simulated results illustrate that the modified PSO algorithm has the potential to converge faster, thus reducing the computational expenses, while maintaining/improving the quality of solution. Finally, the proposed algorithm is used for the design of coupled microstrip line band pass filter which is a computationally expensive process when the design is conducted using evolutionary algorithms and electromagnetic (EM) simulation tools.     

应用于助听器的连续时间滤波器设计

提出了一种采用电流控制传送器(CCCⅡ)构成的连续时间双二阶滤波器电路,该滤波器可以应用于助听器和其他的信号处理设备中,能对任意特定频率的信号进行放大或者衰减,易于实现大规模MOS电路的集成。理论分析和计算机仿真表明所提电路方案正确,是可行的。     

一种基于混合滤波器组的高速高分辨率ADC系统研究

本文是关于基于混合滤波器组的模/数转换系统系列文章的第一篇.首先阐明了基于混合滤波器组的模/数转换系统的原理.然后基于z-s变换和IFFT实现了混合滤波器组的模/数转换系统的设计,设计的混合滤波器组具有的-75dB的混叠误差.最后,首次从理论上证明了时间并行交替式模/数转换系统是混合滤波器组的模/数转换系统的特例的重要结论.     

Design and characterization of a real-time correlator

The design and characterization of a real-time correlator/electrically programmable transversal filter is presented, based on a novel functional multiplying structure in a standard single-level MOS LSI process. The analog information is sampled and held at fixed sites on the chip and the tap weights slide past them; the taps are digitized into 7 bits which control the selection of seven binary area-ratioed MOS capacitors per tap position. The rotation of the tap weights can reduce the effect of tap-weight errors but contributes to fixed pattern noise. Experiments using cascaded chips to build longer filters show excellent transfer-function agreement with theory. Dynamic range of the device is limited primarily by fixed pattern noise. This problem has been modeled and at present about a 45-dB dynamic range has been obtained for the heaviest doped chips when driven by input-signal amplitudes which allow better than 1-percent harmonic distortion. With improvements suggested, significant increases are expected in the dynamic range of the device.     

MOS switched-capacitor filters

In the past several years, much progress has been made in bringing the economies of integrated-circuit technology to bear on the realization of voiceband frequency selective filters. This paper will review one approach to this problem, the use of switched-capacitor techniques. The paper emphasizes the practical aspects of switched-capacitor filter design under the constraints imposed by MOS integrated-circuit technology. The basic operation of switched-capacitor filters is reviewed, followed by a discussion of the properties of the various circuit building blocks in MOS technology. Finally, a summary of several filter organizations which appear to be well suited to switched-capacitor implementation is presented.