Schottky barrier thin-film transistor (SBTFT) with silicidedsource/drain and field-induced drain extension

A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 10⁶ for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications     

Characteristics of the Schottky barriers of two-terminal thin-film Al/nano-Si film/ITO structures

The temperature dependence of the Schottky-barrier height and series resistance of two-terminal thin-film Al/nano-Si film/ITO structures are determined from the current—voltage (I–V) characteristics in the temperature range of 20–150°C. It is found that the form of the I–V characteristic at all investigated temperatures can be described by a model of two Schottky diodes connected back-to-back. For these diodes, the general formula is obtained, which allows the construction of functions approximating experimental curves with high accuracy. Based on this formula, a computational model is built, which generalizes the theoretical data obtained by S.K. Cheung and N.W. Cheung widely used for analyzing the I–V characteristics of single Schottky diodes. A technique is developed for calculating the Schottky-barrier heights in a system of two Schottky diodes connected back-to-back, their ideality factors, and the series resistance of the system. It is established that the barrier heights in the investigated temperature range are ~1 eV. According to the temperature dependence of the barrier height, such large values result from the presence of a SiO _x (0 ≤ x ≤ 2) oxide layer at the nanoparticle boundaries. Charge carriers can overcome this layer by means of thermal excitation or tunneling. It is established that the intrinsic Schottky-barrier height of the Al/nc-Si film and nc-Si film/ITO junctions is ~0.1 eV. The activation dependences of the series resistance of the Al/nc-Si film/ITO structures and impedance spectra show that combined electric-charge transport related to ionic and electronic conductivity takes place in the structures under study. It is shown that the contribution of the electronic conductivity to the total transport process increases as the sample temperature is raised.     

Indium-tin oxide/Si contacts with In- and Sn-diffusion barriers in polycrystalline Si thin-film transistor liquid-crystal displays

Indium and tin were used as the diffusion barrier between indium-tin oxide (ITO) and polycrystalline-silicon layers to reduce the contact resistance. The ITO/Si contacts may be adopted in thin-film transistor liquid-crystal displays (TFT-LCD) to reduce the number of fabrication steps. With In and Sn layers, contact-resistance values of 5 × 10⁻³−4×10⁻³ Ωcm² were obtained. These values were higher than those of the conventional ITO/Mo/Al/Si contacts (3×10⁻⁵−4 × 10⁻⁴ Ωcm²) but lower than the values obtained from ITO/Si contacts (about 1×10⁻² Ωcm²). The Sn was stable after annealing, but In diffused into Si and lost its function as the diffusion barrier.     

Three-dimensional simulation of impurity diffusion in thin-film diffusion barriers

Three-dimensional (3D) simulation of combined lattice and grain-boundary diffusion of impurities in thin-film diffusion barriers for eemiconductor device metallizations is performed. Calculated results of impurity concentration profiles demonstrate quantitatively an obvious underestimation of the frequently used two-dimensional (2D) analysis with respect to the influence of film geometry and grain-boundary diffusion coefficient. As for the average concentration at the backside of diffusion barriers, approximately a factor of two difference between the 2D and 3D simulation results is found over an interesting range of times and grain size structures. Graphs for predicting the effectiveness of diffusion barriers are presented with several normalized parameters associated with position and time. Particular application examples of aluminum diffusion in titanium nitride films justify the use of this material as an effective diffusion barrier in silicon microelectronic devices.     

Modification of GaAs Schottky barriers using a-Si:H interfaciallayers

The electrical characteristics of metal/a-Si:H/n-GaAs diode structures were studied in order to investigate the role of the a-Si:H and the claim of no barrier at the GaAs/a-Si:H interface. Diodes were fabricated using a-Si:H layers between 30 and 1920 Å thick, with Al and Mg metallization, and the current-voltage and capacitance-voltage characteristics were examined. Rectifying Schottky barriers were formed at Al/a-Si:H junctions, while good ohmic contacts were formed at Mg/a-Si:H junctions, enabling effects due to the metal/a-Si:H and a-Si:H/GaAs interface to be isolated. A dramatic increase in the forward turn-on voltage was observed as the thickness of the a-Si:H layer increased. The diode behavior can be explained by considering three effects in series: (1) an a-Si:H/GaAs barrier of about 0.6 eV, consistent with Fermi-level pinning in GaAs; (2) a metal/a-Si:H barrier, dependent on the metallization; and (3) space-charge-limited current (SCLC) in the bulk a-Si:H. The SCLC effectively gives rise to a voltage-dependent resistance and causes the increased turn-on voltages     

Current-source a-Si:H thin-film transistor circuit for active-matrix organic light-emitting displays

In this letter, we describe a four thin-film-transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology. This circuit can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The experimental results indicated that, for TFT threshold voltage shift as large as /spl sim/3 V, the output current variations can be less than 1 and 5% for high (/spl ges/0.5 /spl mu/A) and low (/spl les/0.1 /spl mu/A) current levels, respectively. This circuit can potentially be used for the active-matrix organic light-emitting displays (AM-OLEDs).     

Trap distribution in gold-refractory/GaAs Schottky barriers

Interfacial and bulk traps are shown to be introduced in GaAs Schottky barriers as a result of metal deposition. Majority carrier and minority carrier traps are correlated with degradation in field effect transistor properties. The interface traps are present in both the sputtered and electron beam evaporated layers.     

A new poly-Si thin-film transistor with poly-Si/a-Si double activelayer

A new poly-Si TFT employing a rather thick poly-Si (400 Å)/a-Si(4000 Å) double active layer is proposed and fabricated in order to improve the stability of poly-Si TFT without sacrificing the on/off current ratio. Due to the thick double layer the on-state drain current of the proposed TFT flows through a broad current path near the drain junction so that the current density in the drain depletion region where large electric field is applied is considerably reduced. Consequently, additional trap state generation attributed to large current flow and large electric field in poly-Si channel decreases and the electrical stability of the proposed device has been considerably improved     

Hydrogenated amorphous silicon thin-film transistor on plastic with an organic gate insulator

We developed a high-performance, hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) on plastic substrate using an organic gate insulator. The TFT with a silicon-nitride (SiN/sub x/) gate insulator exhibited a field-effect mobility of 0.3 cm/sup 2//Vs and a threshold voltage of 5 V. On the other hand, an a-Si:H TFT with an organic gate insulator of BCB (benzocyclobutene) has a field-effect mobility of 0.4 cm/sup 2//Vs and a threshold voltage of 0.7 V. The leakage currents through the gate insulator of an a-Si:H TFT with an organic gate insulator is about two orders of magnitude lower than that of an a-Si:H TFT with a SiN/sub x/ gate insulator.     

A new a-Si:H thin-film transistor pixel circuit for active-matrix organic light-emitting diodes

We propose a new pixel circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs), composed of three switching and one driving TFT, for active-matrix organic light-emitting diodes (AMOLEDs) with a voltage source method. The circuit simulation results based on the measured threshold voltage shift of a-Si:H TFTs by gate-bias stress indicate that this circuit compensates for the threshold voltage shifts over 10000 h of operation.     

Schottky barriers fabricated on glow discharge A-Si:H films deposited under bias

Hydrogenated amorphous silicon films were deposited in a three electrode dc glow discharge system under the substrate bias. The composition of the films, using infrared spectroscopy, has been investigated. The photovoltaic parameters of the fabricated Au and Pt Schottky barrier structures have been measured. The purpose of this study was to determine if polarization of the substrates influence the properties of the deposited a-Si:H films. At present with the EECS Department, University of Santa Clara, Santa Clara, California 95053. At present with the Eaton Corporation, Milwaukee, Wisconsin 53216.     

Feasibility of an Ag-alloy film as a thin-film transistor liquid-crystal display source/drain material

The Ag-alloy films have been investigated as source/drain materials applicable to thin-film transistor liquid-crystal displays (TFT-LCDs). The Ag-alloy consisting of 0.9at.%Pd, 1.7at.%Cu (designated APC) showed a resistivity that was lower than one-half that of AlNd. It also had good contact characteristics with amorphous Si (a-Si). In addition, the Ag/Si was stable after heating to above 700°C, requiring no diffusion barrier to prevent reaction between Ag and Si. Pure Ag films deposited on glass by DC magnetron sputtering showed severe hillock formation, hole growth, and agglomeration upon annealing in air. In comparison, the APC-alloy film exhibited improved resistance to agglomeration. Further, inverted-staggered back-channel-etch hydrogenated amorphous silicon (a-Si:H) TFTs using an APC-alloy film as a source/drain material had a threshold voltage of 4 V. A structure of single layers of gate-APC alloys and source/drain-APC alloys leads to lower costs and productivity improvements of large-area, high-resolution, active-matrix LCDs, such as 40-in. size panels through process simplification.     

Observation of Negative Differential Conductance in a Reverse-Biased Ni/Ge Schottky Diode

In this letter, we report the experimental observation of negative differential conductance (NDC) in a Ni/Ge Schottky diode. With the aid of theoretical models and numerical simulation, we show that, at reverse bias, electrons tunnel into the high electric field of the depletion region. This scatters the electrons into the upper valley of the Ge conduction band, which has a lower mobility. The observed NDC is hence attributed to the transferred-electron effect. This shows that Schottky contacts can be used to create hot electrons for transferred-electron devices.      

High-speed Ga0.47In0.53As MISIMphotodetectors with dielectric-assisted Schottky barriers

A technique is described for fabricating high-speed metal-insulator-semiconductor-insulator-metal (MISIM) photodetectors for high-speed fiber-optic systems. These devices make use of a Langmuir-Blodgett film enhanced Schottky barrier to achieve broadband linear response to 13 GHz at low bias voltage (5 V) with ~0.9 A/W external responsivity, 15 V breakdown voltage, and ~2 μA dark current. A gain of about 2 and a 5% tail in the temporal response are analyzed. The needed bias and the device processing are compatible with those for integrated receivers     

Effect of ultrasonic loading on current in Mo/n-n +-Si with Schottky barriers

The results obtained in experimental studies of the operation of silicon Schottky diodes subjected to ultrasonic loading (oscillations frequency of 9.6 MHz; intensity of longitudinal waves as high as 0.7 W/cm²) are reported. A reversible acoustically induced decrease in the Schottky barrier height (to 0.13 V) and an increase in the saturation and reverse current (by as much as 60%) are observed. It is shown that ultrasound does not affect the ideality factor of the diodes and the tunneling component of the reverse current. The process of electron transport is considered within the context of the model of an inhomogeneous Schottky barrier; it is shown that the observed effects can be related to the acoustically induced ionization of defects, which are located at the metal-semiconductor interface.     

Inhomogeneous Ni/Ge Schottky barriers due to variation in Fermi-level pinning

To achieve high performance Ge nMOSFETs it is necessary to reduce the metal/semiconductor Schottky barrier heights at the source and drain. Ni/Ge and NiGe/Ge Schottky barriers are fabricated by electrodeposition using n-type Ge substrates. Current (I)–voltage (V) and capacitance (C)–voltage (V) and low temperature I–V measurements are presented. A high-quality Schottky barrier with extremely low reverse leakage current is revealed. The results are shown to fit an inhomogeneous barrier model for thermionic emission over a Schottky barrier. A mean value of 0.57 eV and a standard deviation of 52 meV is obtained for the Schottky barrier height at room temperature. A likely explanation for the distribution of the Schottky barrier height is the spatial variation of the metal induced gap states at the Ge surface due to a variation in interfacial oxide thickness, which de-pins the Fermi level.     

Hydrogenation of polysilicon thin-film transistor in a planarinductive H2/Ar discharge

A planar inductive discharge is used to hydrogenate polysilicon thin-film transistors (poly-Si TFTs). Experimental results indicate that inductive discharges operate at higher plasma densities, thereby capable of shortening the hydrogenation time, in addition, to promote the ionization of hydrogen, Ar gas is also introduced to H₂ plasma during hydrogenation. Furthermore, we discuss the mechanism of Ar enhanced hydrogenation and the characteristics of H₂/Ar mixed plasma. Moreover, the post-hydrogenation anneal is utilized to further enhance passivation efficiency and improve the reliability of poly-Si TFTs     

Simulation analysis of the DC current gain in an n-p-n a-Si:H/SiGe/Si heterojunction bipolar transistor

This paper presents the results of a simulation study focused on the evaluation of the DC characteristics of an n-p-n SiGe-based heterojunction bipolar transistor (HBT) performing an extremely thin n⁺ hydrogenated amorphous silicon (a-Si:H) emitter. The a-Si:H(n)/SiGe(p) structure exhibits an energy gap difference of approximately 0.8 eV mostly located at the valence band side and this results in an optimal configuration for the emitter/base junction to improve the emitter injection efficiency and thus the device performance.Considering a 20% Ge uniform concentration profile in the base region, simulations indicate that the DC characteristics of an a-Si:H/SiGe HBT are strictly dependent on two essential geometrical parameters, namely the emitter width and the base width. In particular, the emitter thickness degrades device characteristics in terms of current handling capabilities whereas higher current gains are obtained for progressively thinner base regions. A DC current gain exceeding 9000 can be predicted for an optimized device with a thin emitter and a 10 nm-thick, doped base.     

A common-gate CMOS inverter with n-channel amorphous silicon thin-film transistor formed on a crystalline PMOSFET

A common-gate complementary metal-oxide-semiconductor (CMOS) inverter consisting of an n-channel amorphous silicon (a-Si:H) thin-film transistor on top of 1.2 μm high Al gate of the crystalline silicon p-channel metal-oxide-semiconductor (PMOS) transistor has been achieved successfully. The success of this inverter demonstrates the feasibility of depositing 3500 Å thick amorphous silicon material on a surface with roughness in the order of 1.2 μm. It is found that growing an undoped amorphous silicon layer before the deposition of SiN_x insulator is necessary to avoid the permanent destruction of the underlying PMOS due to the stress imposed by the SiN_x. The vertical integration of crystalline silicon and amorphous silicon devices to form three-dimensional circuits is a promising technique for future applications in high density memory cell and neural network image sensors.     

Monte Carlo simulation of electron transport efficiency of an InGaAs/InP hot-electron transistor

Electron transport efficiency of an InGaAs/InP hot-electron transistor (HET) is determined by a Monte Carlo method including alloy scattering in an InGaAs base. Results are compared with those of a GaAs/AlGaAs HET. It is found that the InGaAs/InP HET offers a higher current gain than that of a GaAs/AlGaAs HET by an order of magnitude.