GaAs Ultra-High-Speed Prescaler/Phase Frequency Comparator Using LSCFL (Short Paper)

A high-speed, low-power prescaler/phase frequency comparator (PFC) medium scale integration (MSI) circuit for a phase-locked stable oscillator is designed and fabricated using GaAs MESFET low-power source-coupled FET logic (LSCFL) circuitry. The construction of the 1/64 frequency divider prescaler/PFC is designed to obtain high-speed and low-power operation. The fabrication process used is buried p-layer SAINT with a 0.5-µm gate length. The fabricated prescaler/PFC MSI circuit, mounted on a newly developed high-frequency package, operates up to 7.6 GHz with a power dissipation of 730 mW.     

A 5-mA 1-GHz GaAs dual-modulus prescalar IC

A 1-GHz GaAs dual-modulus divide-by-128/129 prescalar IC with current drain of only 5 mA has been developed. Its current drain is one-sixth that of commercially available Si bipolar ICs used in 800-MHz band mobile radio systems. Five-level series gate low-power source-coupled FET logic (LSCFL) and the 0.50-/spl mu/m gate buried P-layer SAINT (BP-SAINT) process technology have been used to achieve this small current drain together with high-speed operation. A high-speed divide-by-4/5 modulus divider (3.1 GHz, 13 mA) and divide-by-32 divider (6.1 GHz, 19 mA) has also been designed and fabricated. These prescalars are suitable for use as synthesizers in mobile communication systems.     

A 2500 gate bipolar macrocell array with 250 ps gate delay

An oxide-isolated walled-emitter structure has been developed to obtain high performance and high packing density. Using this process, a macrocell array having 2500 equivalent gates has been fabricated. A gate delay of 250 ps with a 1 mA current switch has been achieved. Special circuitry and macros have been incorporated on the LSI to enhance diagnostic capability at both the chip and the system levels. A pin array package with /spl theta//SUB JA//spl les/4/spl deg/C/W has been developed for the LSI chip.     

Deep-submicron HEMT technology

The current status of HEMT technology and its impact on computers and communications are presented, focusing on the advantages of the device in the deep-submicrometre dimensional range, self-aligned HEMT processing, and the HEMT LSI implemented in supercomputer and communication systems.

Ultra-low-noise HEMTs are already commercially available in satellite communications, and have made a great impact in expanding the broadcasting satellite market. For ultra-high-speed digital LSI applications the 1 k gate bus-driver logic LSI has been developed to demonstrate high-speed data transfer in a high-speed parallel processing supercomputer system at room temperature, operating at 10·92 Gflops. The 7 k gate asynchronous transfer mode (ATM) switch LSI has alsi been developed to evaluate high-speed data switching for Broadband Integrated Service Digital Network (B-ISDN). The maximum operation frequency was 1·2 GHz at room temperature. The single-chip throughput was 9·6 Gb/s and a throughput of 38·4 Gb/s was achieved in a 4 × 4 ATM switching module.     

A gigabit MOS logic circuit with buried channel MOSFETs

An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.     

A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO

An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6-μm high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm×4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s     

High-speed frequency dividers with quasi-normally-off GaAs MESFETs

Master-slave binary frequency dividers have been designed and implemented with enhancement-mode GaAs MESFETs by using the so-called LPFL logic approach. A wide range of speed-power performances has been observed: a maximum toggle frequency of 2.8 GHz at P = 15 mW/gate on a dual-clocked frequency divider and an fc,max of 1.73 GHz at Pxtpd = 1 pJ/gate on a single-clocked one. The high-speed performance obtained corresponds to a propagation delay of 145 ps for the constituent NOR-OR gates of fan-in/fan-out = 4/3, and it is made possible by careful optimisation of circuit design parameters.     

A self-aligned gate III-V heterostructure FET process forultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8×8 multiplier/accumulator, and a 4500-gate 16×16 complex multiplier have been demonstrated using enhancement-mode n⁺ -(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1-μm gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 μm of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained     

A high-speed, low-power divide-by-4 frequency divider implementedwith AlInAs/GaInAs HBT's

The authors describe the first frequency divider demonstrated using AlInAs/GaInAs heterojunction bipolar transistors (HBTs). The divider (a static 1/4 divider circuit) operates up to a maximum frequency of 17.1 GHz, corresponding to a gate delay of 29 ps for a bilevel current-mode logic (CML) gate with a fan-out of 2, and a total power consumption of 67 mW (about 4.5 mW per equivalent NOR gate). These results demonstrate the potential of AlInAs/GaInAs HBTs for implementing low-power, high-speed integrated circuits     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

High-Speed Digital Switching Technology Using Space-Division-Switch LSI's

NTT is planning a high-speed broad-band switching network that offers high-speed digital and 4 MHz video services. This paper discusses the hardware design of the high-speed space-division digital switching network and requirements for a switch LSI. In addition, the design and measured performance of a 32 × 32 CMOS space-division-switch LSI are described. In this network, video signals are converted into 32 Mbit/s digital signals by band-compression technology. In order to switch such digital signals, space-division switches are more advantageous than time-division switches. This is because time-division switches cannot multiplex many channels at that bit rate. Furthermore, the use of the space-division-switch LSI is the most effective way to miniaturize the switching system.     

Molybdenum gate MOS applied to an AM/FM digital frequency synthesizer

An n-channel molybdenum self-aligned gate MOS technology has been developed and applied to an AM/FM digital frequency synthesizer. A high-frequency programmable divider operating at 180 MHz has been achieved by the use of molybdenum, low parasitic capacitance structures and zero-threshold MOS transistors, while maintaining conventional design rules. Molybdenum gate MOS has enabled the realization of a single-chip system, which consists of a directly programmable divider for the AM/FM local oscillators, a reference counter, a phase comparator, a circuit for dial tuning, and memories for storing the frequencies for 16 stations. A differential comparator has been fabricated on the LSI chip to simplify digital tuning in the receiver.     

30-ps 7.5-GHz GaAs MESFET macrocell array

An ECL-compatible GaAs 250-gate macrocell array has been successfully designed and fabricated using a three-level series gate low-power source-coupled FET logic (LSCFL) and a newly developed 0.4- mu m-gate self-aligned MESFET process. The unloaded propagation delay time was 30 ps/gate at a 2.4-mW/gate power dissipation. The loaded delay time with fan-out=3 and a 2-mm line length was as fast as 74 ps. The flip-flop toggle frequency was 7.5 GHz. A 2*2 asynchronous transfer mode (ATM) switch circuit was constructed on the macrocell array, and a maximum operation frequency of 2 GHz was achieved.<>     

A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATMswitch based on scalable distributed arbitration

This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4×2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSI's. To increase the LSI throughput and reduce the power consumption, we used 0.25-μm CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSI's, an 8×8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size     

High-speed low-power logic ICs using quasi-normally-off GaAs MESFETs

A digital approach, called `low pinchoff-voltage FET logic' (LPFL), is proposed for high-speed LSI circuit applications. It makes use of `quasi-normally-off' GaAs MESFETs, i.e., Schottky-gate devices operating in enhancement model with a pinchoff-voltage ranging between -0.2 and +0.2 V. Such a V/SUB P/ range is about twice that tolerated by conventional normally-off circuits and thus higher fabrication yields can be routinely achieved. Performances which can be achieved with this approach have been tested by means of a single-clocked frequency divider circuit fabricated with MESFETs of 1 /spl mu/m/spl times/20 /spl mu/m gate geometry.     

A picosecond-accuracy, 700-MHz range, Si bipolar time intervalcounter LSI

A picosecond-accuracy digital vernier-based single-chip time interval counter (TIC) LSI applicable to timing calibration in state-of-the-art high-speed LSI test systems is described. Jitter performance is improved to three times higher than in conventional circuitry by using a new skew detection circuit that is insensitive to the jitter caused by metastable transitions in flip-flops. All the hardware except the signal sources has been integrated on a Si bipolar 2.5 K gate array LSI by developing fully digitally processes heat-signal and trigger control circuits. The chip is mounted on a dedicated ceramic package employing coplanar lines with a 3-GHz bandwidth. Overall performance achieves 2.3-ps standard deviation, ±3-ps linearity, zero-skew offset of ±2.7 ps, and an equivalent input slew time of 33.6 ps/V at input clock rates up to 700 MHz     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

MSI High-Speed Low-Power GaAs Integrated Circuits Using Schottky Diode FET Logic

A new planar high-density (10/sup -3/ mm/sup 2//gate) GaAs IC technology has been used for fabricating MSI digital circuits containing up to 75 gates/chip. These digital circuits have potential application for gigabit microwave data transmission and processor systems. The circuits consist of Schottky diode FET logic NOR gates, which have provided propagation delays in the 75-200-ps range with dynamic switching energies as low as 27 fJ/gate on ring oscillator structures. Power dissipation levels are compatible with future LSI/VLSI extensions. Operation of D flip-flops (DFF) as binary ripple dividers (/spl divide/2-/spl divide/8) was achieved at 1.9-GHz clock rates, and an 8:1 full-data multiplexer and 1:8 data demultiplexer were demonstrated at 1.1-GHz clock rates. This corresponds to equivalent propagation delays in the 100-175-ps range for these MSI circuits. Finally, a 3x3 parallel multiplier containing 75 gates functioned with a propagation delay of 172 ps/gate and with average gate power dissipations of as low as 0.42 mW/gate.     

A 920 gate DSA MOS masterslice

A DSA MOS (diffusion self-aligned MOS) masterslice circuit with up to 920 gates and a delay of 3 ns per gate has been developed for random logic computer circuits, utilizing the performance and economical advantages of the LSI masterslice approach. To attain high packing density and high speed with conventional design rules, the DSA MOSFET technology has been used for the basic device. The chip comprises 50 by 16 gate cells and 116 input/output buffers. This LSI chip is two to three times better than bipolar S-TTL in packing density and is comparable in propagation delay time. As an example of an LSI device obtained through customized metallization, an 8 bit ALU is described which has an average delay time of 3 ns and a power dissipation of 3 W.     

1 Gbit/s, 32*32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.<>