应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

基于应变Si/SiGe的CMOS电特性模拟研究

提出了一种应变Si/SiGe异质结CMOS结构,采用张应变Si作n-MOSFET沟道,压应变SiGe作p-MOSFET沟道,n-MOSFET与p-MOSFET采用垂直层叠结构,二者共用一个多晶SiGe栅电极.分析了该结构的电学特性与器件的几何结构参数和材料物理参数的关系,而且还给出了这种器件结构作为反相器的一个应用,模拟了其传输特性.结果表明所设计的垂直层叠共栅结构应变Si/SiGe HCMOS结构合理、器件性能提高.     

一种适合制作CMOS的SiGe PMOSFET

在通常适合于制作埋沟SiGe NMOSFET的Si/弛豫SiGe/应变Si/弛豫SiGe缓冲层/渐变Ge组分层的结构上,制作成功了SiGe PMOSFET.这种SiGe PMOSFET将更容易与SiGe NMOSFET集成,用于实现SiGe CMOS.实验测得这种结构的SiGe PMOSFET在栅压为3.5V时最大饱和跨导比用作对照的Si PMOS提高约2倍,而与常规的应变SiGe沟道的器件相当.     

应变Si/SiGe沟道功率UMOSFET的模拟分析

提出一种应变Si/SiGe UMOSFET结构,并与Si-UMOSFET器件的电流-电压特性进行比较;对SiGe区域在UMOSFET器件中的不同厚度值进行静态电学仿真。应变Si/SiGe异质结能够有效地提高沟道区载流子的迁移率,增大IDS,降低Vth及器件的Ron;且应变异质结与载流子有效传输沟道距离的大小,对器件的Vth、Isat、V(BR)DSS及电流-电压特性都有较大的影响。因此在满足击穿电压要求的基础上,应变Si/SiGe沟道异质结的UMOSFET相对Si-UMOSFET在I-V特性和Ron方面有较大的改进。     

一种新颖的应变Si沟道 pMOSFET制作技术

在应变Si沟道异质结场效应晶体管(HFET)制作过程中,引入分子束外延(MBE)低温Si(LT-Si)技术,大大减少了弛豫SiGe层所需的厚度.TEM结果表明,应变Si层线位错密度低于106cm-2.原子力显微镜(AFM)测试表明,其表面均方粗糙度小于1.02nm.器件测试结果表明,与相同条件下的体Si pMOSFET相比,空穴迁移率提高了25%.     

一种新颖的应变Si沟道 pMOSFET制作技术

在应变Si沟道异质结场效应晶体管(HFET)制作过程中,引入分子束外延(MBE)低温Si(LT-Si)技术,大大减少了弛豫SiGe层所需的厚度.TEM结果表明,应变Si层线位错密度低于106cm-2.原子力显微镜(AFM)测试表明,其表面均方粗糙度小于1.02nm.器件测试结果表明,与相同条件下的体Si pMOSFET相比,空穴迁移率提高了25%.     

双应变SiGe/Si异质结CMOS的设计及其电学特性的Medici模拟

本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成.     

一种新颖的应变Si沟道pMOSFET制作技术

在应变Si沟道异质结场效应晶体管（HFET）制作过程中，引入分子束外延（MBE）低温Si (LT-Si）技术，大大减少了弛豫SiGe层所需的厚度. TEM结果表明，应变Si层线位错密度低于1E6cm-2.原子力显微镜（AFM）测试表明，其表面均方粗糙度小于1.02nm.器件测试结果表明，与相同条件下的体Si pMOSFET相比，空穴迁移率提高了25%.     

薄虚拟SiGe衬底上的应变Si pMOSFETs

成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT-Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe衬底的应变弛豫度为85%,表面平均粗糙度仅为1.02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.     

Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟,给出了以提高跨导为目标的Si/SiGe PMOSFET优化设计方法,包括栅材料的选择、沟道层中Ge组分及其分布曲线的确定、栅氧化层及Si盖帽层厚度的优化和阈值电压的调节,基于此已研制出Si/SiGe PMOSFET器件样品.测试结果表明,当沟道长度为2μm时,Si/SiGe PMOS器件的跨导为45mS/mm(300K)和92mS/mm(77K),而相同结构的全硅器件跨导则为33mS/mm(300K)和39mS/mm(77K).     

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.     

Hole and electron mobility enhancement in strained SiGe verticalMOSFETs

We have fabricated strained SiGe vertical P-channel and N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 μm without sophisticated lithography and the whole process is compatible with a regular CMOS process. The enhancement for the hole and electron mobilities in the direction normal to the growth plane of strained SiGe over that of bulk Si has been demonstrated in this vertical MOSFET device structure for the first time. The drain current for the vertical SiGe MOSFETs has been found to be enhanced by as much as 100% over the Si control devices and the drain current for the vertical SiGe NMOSFETs has been enhanced by 50% compared with the Si control de, ices on the same wafer. The electron mobility enhancement in the normal direction is not as significant as that for holes, which is in agreement with theoretical predictions     

Strained Si/SiGe MOS technology: Improving gate dielectric integrity

Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance gains in short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to the lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.     

Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs

A fundamental understanding of the mechanisms responsible for the dependence of hole mobility on SiGe channel layer thickness is presented for channel thicknesses down to 1.8 nm. This understanding is critical to the design of strained SiGe p-MOSFETs, as lattice mismatch limits the thickness of SiGe that can be grown on Si and as Ge outdiffusion during processing reduces the Ge fraction. Temperature-dependent measurements are used to extract the phonon-limited mobility as a function of SiGe channel thickness for strained Si_0.57Ge_0.43 heterostructures on bulk Si. The hole mobility is shown to degrade significantly for channel thickness below 4 nm due to a combination of phonon and interface scattering. Due to the finite nature of the quantum-well barrier, SiGe film thickness fluctuation scattering is not significant in this structure for channel thickness greater than 2.8 nm.     

深亚微米应变SiGe沟PMOSFET特性模拟

为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si Ge沟PMOSFET具有很大的性能提高潜力     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.     

A novel low-voltage N-channel heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) with p-type doped SiGe body

A novel N-channel Si/SiGe heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) has been proposed and fabricated. The Si/SiGe N-HDTMOS consists of an unstrained surface Si channel and heavily p-type doped SiGe body. The potential of the conduction band edge of the surface Si channel can be lowered by introducing a heavily p-type doped SiGe layer into a suitable position in the body region. As a result, the N-HDTMOS shows a threshold voltage reduction and a body effect factor (/spl gamma/) enhancement while keeping high doping concentration in the SiGe layer. The fabricated SiGe N-HDTMOS exhibits superior properties, that is, 0.1 V reduction of V/sub th/, 1.5 times enhancement of /spl gamma/, and 1.3 times saturated current, as compared with those of Si N-DTMOS.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.