量程自整定高精度频率测量的FPGA实现

数字频率计是一种应用十分广泛的电子测量仪表,针对宽频率范围被测信号频率测量应用需求,提出并实现了一种基于FPGA的自动量程切换高精度数字频率计的设计方法。通过构建测频控制器、闸门同步生成器、量程自动切换等模块,并采用Verilog HDL语言进行描述,运用自顶向下的数字系统设计方法实现了宽频率范围频率测量的量程自动切换。在Xilinx公司的XUPV5-LX110T开发板上进行了测试,给出了系统后仿真波形。结果表明目标系统能根据被测信号频率范围进行自动量程切换,实现高精度频率测量,测量精度不低于10-7,有效提高系统稳定性和抗电磁干扰能力。     

获取目标最佳极化算法的FPGA实现

根据带门限的序列Jacobi方法,提出了一种实时获取目标最佳极化的FPGA实现方法。该方法精简了对待求矩阵最大非对角元素的搜索过程,并在FPGA中采用并行结构的运算模块设计,优化了有限状态机(FSM)的执行时序,从而避免了CORDIC算法繁琐的迭代过程,减少了程序运行时间。FPGA实现结果表明,该方法的执行速度比CORDIC算法至少提高了21%,具有较高的实时性。     

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day.     

The use of field programmable gate array （FPGA） in direct torque control of induction motor

In this paper, the feasibility of embedding the direct torque control （DTC） of an induction machine into field programmable gate arrays （FPGA） is investigated. DTC of an induction machine is simulated in a MATLAB/Simulink environment using a Xilinx system generator. The resulting design has a flexible and modular structure where the designer can customize the hardware blocks by changing the number of inputs, outputs, and algorithm when it is compared to the designs implemented using classical microcontrollers and digital signal processors. With its flexibility, other control algorithms can easily be programmed and embedded into the FPGA. The above system has been implemented on Xilinx Spartan 3A DSP FPGA controller. Simulation and experimentation have been performed to prove the validity of the proposed methodology.     

复杂物理模型仿真的多进程流水线方法*

介绍了一种利用并行运算解决高维度、非线性、强耦合系统模型仿真问题的方法。该方法以现场可编程门阵列(FPGA)技术为依托,在流水线设计思想的基础上,利用所提出的流水线算子概念实现了从非线性常微分方程向流水线数据通路的转换过程。该方法为在FPGA上设计模拟各种复杂物理模型的流水线数据通路提供了一种简单有效的解决方案。     

应用于硅微谐振式传感器的等精度频率计设计

针对传统频率测量中存在的弊端,利用等精度测频原理,采用现场可编程门阵列(FPGA)设计实现了等精度频率计。通过FPGA对同步门的控制,使被测信号和标准信号在闸门时间内同步,消除了量化误差,提高了测量精度,实现了在整个测试频段内测量精度不随被测信号频率的高低而发生变化,即实现了等精度测量。实验证明:采用该频率计测量标准信号频率的相对误差数量级为10-6,测量谐振式传感器在温漂下的输出频率的变化稳定在±1 Hz,而且实现了谐振式传感器在红外辐射下频率的动态跟踪。     

神经元网络的FPGA硬件仿真方法*

提出了一种利用FPGA对生物神经元网络进行硬件仿真的方法.该方法充分考虑了多进程流水线模型中各神经元状态输出的时序问题,设计了节点选择器完成对流水线数据通路输出数据的保存和选择功能,实现了多状态耦合情况下精确的仿真方法.最后,利用该方法对Morris-Lecar神经元网络模型进行了FPGA硬件仿真,再现了Morris-...     

应用单片机和FPGA实现的地雷炸点测试仪

介绍便携式地雷炸点测试仪的硬件结构和软件流程以及FPGA的设计方案。将单片机和现场可编程逻辑器件FPGA结合运用，电路简单，控制容易，可靠性强。     

Extended gate electrode arrays for extracellular signal recordings

We have fabricated arrays of planar gold electrodes arranged in a matrix of 8×8 with active areas ranging from 6 to 30 μm in diameter. An electronic amplification circuitry based on commercial junction field-effect transistors was used where the gold sensor fields act as extended gate electrodes (EGE) of the transistors, which leads to a new approach for long-term extracellular recording systems in vitro. The high input resistance of the amplification circuitry allows the use of small planar bare gold electrodes without further modification which therefore extends the frequency range of the measuring set-up down to the DC-level. The performance of our recording system has been tested using rat cardiac myocytes cultured directly on the device surface. The recorded signals were then compared in shape and size with recordings performed with a similar extracellular measurement set-up based directly on field-effect transistors with non-metallized gate electrodes. By simulations we could show the influence of the electrode capacitance on the time-course and on the size of the measured signals.     

用FPGA实现统筹兼顾 端中的显示RAM控制

本文主要阐述了用FPGA设计显示终端的显示RAM控制器的原理和应用模型,着重介绍图形显示RAM的透明刷新存储设计方法和用FPGA的实现技术。     

基于FPGA的光栅地震检波器信号处理研究

光栅地震检波器是基于光栅检测技术设计的一种新型数字传感器,基于单片机的光栅地震检波器信号处理速度较慢,现场可编程门阵列FPGA时钟频率高,内部延时小,硬件资源丰富,在控制数据采集、转换等方面有着单片机和DSP所无法比拟的优势。为了提高光栅地震检波器的测量精度和分辨力,该文进行了基于FPGA的光栅地震检波器信号处理研究,并将软件细分原则应用于信号处理系统中。该系统基于硬件描述语言Verilog和PicoBlaze软核进行设计,在有效地减小电路板面积的同时,可实现数据的快速采集和高精度测量。     

Modular array structure for non-restoring square root circuit

Square root is an operation performed by the hardware in recent generations of processors. The hardware implementation of the square root operation is achieved by different means. One of the popular methods is the non-restoring algorithm. In this paper, the classical non-restoring array structure is improved in order to simplify the circuit. This reduction is done by eliminating a number of circuit elements without any loss in the precision of the square root or the remainder. For a 64-bit non-restoring circuit the area of the suggested circuit is about 44% smaller than that of a conventional non-restoring array circuit. Furthermore, in order to create an environment for modular design of the non-restoring square root circuit, a number of modules are suggested. Using these modules it is possible to construct any square root circuit with an arbitrary number of input bits. The suggested methodology results in an expandable design with reduced-area. Analytical and simulation results show that the delay of the proposed circuit, for a 64-bit radicand, is 80% less than that of a conventional non-restoring array circuit.     

A novel approach to the placement and routing problems for field programmable gate arrays

This paper presents an artificial neural network (ANN) based parallel evolutionary solution to the placement and routing problems for field programmable gate arrays (FPGAs). The concepts of artificial neural networks are utilized for guiding the parallel genetic algorithm to intelligently transform a set of initial populations of randomly generated solutions to a final set of populations that contain solutions approximating the optimal one. The fundamental concept of this paper lies in capturing the various intuitive strategies of the human brain into neural networks, which may help the genetic algorithm to evolve its population in a more lucrative manner. A carefully chosen fitness function acts in the capacity of a yardstick to appraise the quality of each “chromosome” to aid the selection phase. In conjunction with the migration phase and the chosen fitness function various genetic operators are employed, to expedite the transformation of the initial population towards the final solution. The suggested algorithms have been implemented on a 12-node SGI Origin-2000 platform using the message passing interface (MPI) standard and the neural network utilities provided by MAT Lab software. The results obtained by executing the same are extremely encouraging, especially for circuits with very large number of nets.     

非制冷红外探测器非均匀性的校正方法

两点温度定标校正算法是非制冷红外探测器的有效的非均匀性校正技术。根据焦平面特性和两点算法,提出一种采用两级存储结构的现场可编程门阵列实现途径:流水运算,采用分级存储校正系数和并行结构运算部件。仿真和试验证明:这种方法具有高速、系数存储大容量、可扩展的特点,适合于大阵列非制冷红外焦平面的实时校正。     

多路百兆比以太网接口卡的研制

介绍了一种用于边缘路由器的多路百兆比以大网卡的系统硬件结构和软件实现。该卡利用两片超大规模高速FPGA芯片，同时处理六路全双工百兆比以大网数据的发送和接收，六路数据完全独立。为实现这种多路高速数据之间的独立以及实时、无差错、高质量传输，本文通过硬件体系结构和逻辑设计的方法，给出了这种高速高质量宽带多业务接入的复用解复用算法的实现策略。     

基于FPGA的时差法超声波流量计的设计

设计了一种基于现场可编程门阵列（FPGA）的时差法超声波流量计。主要介绍了系统的硬件组成和实现方法,概述了软件功能和软件设计流程。系统硬件电路为微控制器＋FPGA结构,微控制器是系统的控制核心。利用FPGA的可编程特性和很高的工作频率以及丰富的内部资源设计了包括高速计数器．在内的数字信号处理模块,提高了系统的可靠性和测量精度,并具有良好的硬件可升级性。     

基于自适应控制的光功率计设计

提出了一种具有自适应控制的光功率计系统,该系统采用电路设计和程序控制算法相结合的方法制定了自适应控制激光器的发射功率方案,并用数字电位器调整驱动电流模拟大气信道参数变化所引起电流变化,使系统能够随着大气信道参数的变化自适应地调整发射功率,以保证通信质量。实验以安捷伦8163B光功率计作标准,通过对比分析自适应的光功率控制的线性度较好,相对测量误差小于1%,稳定度比安捷伦8163B光功率计的稳定度高5%。     

Construction of square root factor for solution of the Lyapunov matrix equation

The Lyapunov matrix equation is considered in this paper, where the solution is a nonnegative definite matrix, i.e. a matrix admitting decomposition in square root factors. An algorithm for findings the square root factor without preliminary finding the solution itself is given.