LPCC浮点运算IP核的设计与实现

介绍了线性预测倒谱系数(Linear Prediction Cepstrum Coefficient,LPCC)提取算法,给出该算法的一种浮点IP核实现模型,并详细描述了各个子模块的设计方法。以VHDL作为设计语言,在ISE、ModelSim软件下完成综合和仿真,并在Xilinx Spartan-3 FPGA目标板上实现设计。采用关键路径流水线实现、资源共享等技术进行优化。该IP核计算结果精度高,运算时间短,已经成功应用在嵌入式语音识别系统中。     

43位浮点流水线乘法器的设计

提出一种浮点流水线乘法器IP芯核。该乘法器采用改进的三阶Booth算法减少部分积数目,提出了一种压缩器混用的Wallace树结构压缩阵列,并对关键路径中的5-2压缩器、4—2压缩器和64位CLA加法器进行了优化设计,有效降低了乘法器的延时和面积。经FPGA仿真验证表明,该乘法器运算能力比Altera公司近期提供的同类乘法器单元快15．4％。     

紫外DPS中DA控制器的NiosII-IP核设计与实现

详细介绍了GaN基紫外数字像素探测器(DPS)多通道位串行(MCBS)实现方案中共用DAC设备控制器的自定义IP核的设计和功能实现。文中采用基于嵌入式软核NiosII 处理器可编程片上系统(SOPC)设计方法,通过对以12位数模转换芯片TLV5639为控制对象的IP核的仿真和测试,验证了设计的正确性。实验结果表明设计符合性能要求,基于SOPC的IP核设计方法具有较强实用性和通用性。     

可配置的TFT-LCD控制器IP核的设计

设计实现了一种基于Avalon总线的,显示分辨率和像素深度均可配置的TFT-LCD控制器IP核.根据自顶向下的设计思想,将IP 核进行层次功能划分设计,采用Verilog 硬件描述语言实现该控制器以及它的外围逻辑时序的全部功能.并对IP 核进行仿真验证,最后加入到Nios II系统中,该IP 核经测试效果良好.     

基于AMBA总线的3DES算法IP核的设计与实现

基于AMBA2.0总线,设计并实现了一种使用3DES加密算法的IP核。该设计通过了行为级功能仿真和综合后的时序仿真,成功运用于一款32位浮点DSP芯片中,并且用TSMC 65 nm CMOS工艺实现。目前该IP核已经投入使用,在500 MHz的工作频率下,3DES加/解密速率达到615 Mbps,可以满足大部份系统数据处理的需求。     

8位高速微控制器IP软核的设计与实现

本文介绍了一种8位高速微控制器IP软核的设计,该IP采用哈佛总线和二级流水线,指令集与PIC16F676兼容。本文按照自顶而下的设计流程,首先定义了该MCUIP核的顶层功能和体系结构,然后对各单元模块进行了详细的设计,讲述了IP软核的设计方法及其仿真验证,并对该微控制器的读/写时序进行了分析。     

可配置的SOPC系统TFT-LCD控制器的设计与实现

采用Nios II嵌入式软核构建液晶屏的驱动的解决方案。在FPGA片上系统中调用嵌入式处理器Nios II软核等需要的IP核构建出TFT-LCD控制器,IP 核参数化,可以根据不同LCD屏进行配置;利用C/C++语言进行软件设计和开发,实现图片数据同步、像素数据转换、缓存、数据传输及图像显示。用SignalTap II逻辑分析仪对TFT-LCD控制器进行仿真验证。测试结果显示,所设计的TFT-LCD控制器很好的实现对TFT-LCD的控制,图片显示清晰;该设计方法简便快捷,设计的控制器可以适用于多种型号液晶屏。     

PCI Express协议实现与验证

称为第3代I/O接口技术的PCI Express总线规范的出现,从结构上解决了带宽不足的问题,有着极为广阔的发展前景。基于Verilog HDL硬件描述语言及可综合化设计理念,完成了PCI Express IP核RTL代码的设计。IP核代码使用Verilog HDL语言编写,分模块、分层次地设计了事务层、数据链路层和物理层的逻辑子层,并进行了可综合化设计与代码风格检查。对设计的PCI Express IP核的功能分别从协议层次和应用层次进行了验证。具体实现上,采用Denali公司的PureSuite测试套件对IP核的协议兼容性进行验证,验证范围覆盖了IP核的3个层次以及配置空间,采用QuestaSim仿真工具对IP核的应用层进行验证。仿真结果表明,设计的PCI Express IP核工作正常,性能优良。     

PCI总线主控制器IP的设计

本文讨论一个PCI总线主控制器IP核的设计与验证，描述了该IP核的控制通路和数据通路设计、电路的功能仿真、综合以及验证等过程。结果表明，该IP核在功能和时序上符合PCI技术规范2．2版本，达到了预定的目标。     

Enhancing Accuracy and Dynamic Range of Scientific Data Analytics by Implementing Posit Arithmetic on FPGA

The high performance, power efficiency and reconfigurable characteristic of FPGA attract more and more attention in big data processing. In scientific data analytics, besides the consideration of computing performance, accuracy of the results and dynamic range of data representation are critical features that must be considered. At present, the floating-point IP cores in FPGA design use IEEE standard for floating-point arithmetic – IEEE 754. For FPGA based scientific data application, improving existing floating-point IP cores is a significant way to obtain better results. Posit is a floating-point arithmetic format first proposed by John L. Gustafson in 2017. In posit, the variable precision and efficient representation of exponent contribute a higher accuracy and larger dynamic range than IEEE 754. This work researches on the FPGA implementation of posit arithmetic for extending floating-point IP cores for FPGA based scientific data analytics. We design the logic for hardware implementation and implement it on FPGA. We compare the precision representation, dynamic range and performance of implemented posit FPU (Floating-Point Unit) with IEEE 754 floating-point IP cores. Posit exhibits better superiority in precision representation and dynamic range than IEEE 754, and through further optimization of the implementation, posit can be a good candidate for floating-point IP cores.

     

基于FPGA的数字脉冲压缩系统实现

针对采用线性调频信号的宽带雷达系统,完成单通道高速数据采集和数字脉冲压缩系统的工程实现。系统使用ADS5500完成14位6、0 MSPS的数据采集,使用FPGA实现1 024点的数字脉冲压缩。脉冲压缩模块采用快速傅里叶变换IP核进行设计,可以在脉冲压缩的不同阶段对其进行复用,分别完成FFT和IFFT运算,从而使硬件规模大大减少。系统采用块浮点数据格式以提高动态范围,同时减小截断（或舍入）误差对输出信噪比的影响。     

Privacy-Preserving Data Packet Filtering Protocol with Source IP Authentication

Packet filtering allows a network gateway to control the network traffic flows and protect the computer system. Most of the recent research works on the filtering systems mainly concern the performance, reliability and defence against common network attacks. However, since the gateway might be controlled by red an untrusted attacker, who might try to infer the identity privacy of the sender host and mount IP tracking to its data packets. IP spoofing is another problem. To avoid data packets to be filtered in the packet filtering system, the malicious sender host might use a spoofed source IP address. Therefore, to preserve the source IP privacy and provide source IP authentication simultaneously in the filtering system is an interesting and challenging problem. To deal with the problem, we construct a data packet filtering scheme, which is formally proved to be semantic secure against the chosen IP attack and IP guessing attack. Based on this filtering scheme, we propose the first privacy-preserving packet filtering system, where the data packets whose source IP addresses are at risk are filtered, the privacy of the source IP is protected and its correctness can be verified by the recipient host. The analysis shows that our protocol can fulfil the objectives of a data packet filtering system. The performance evaluation demonstrates its applicability in the current network systems. We also presented a packet filtering scheme, where the data packets from one subnet can be filtered with only one filter policy.     

SoC芯片中基于统计分析的浮点到定点转换方法

在通信、语音、图像处理等数字信号处理应用系统中一般使用浮点算法.为降低硬件成本、功耗,在定点硬件架构上实现浮点算法成为一种有效的解决方案.在定点SoC(System on Chip)芯片中,为达到性能、成本、功耗的平衡,常采用定点近似算法和硬件加速方案对浮点数字信号处理算法进行转换和优化.因此,需要在制造费用、功耗、性能等诸多限制下,将浮点算法转换成定点数近似算法.本文提出了一种基于定点SoC芯片的浮点到定点转换方法.首先,本文引入硬件加速模块参数和转换参数完成浮点算法到定点算法的转换,然后使用本文提出的r通过信噪比对定点数近似算法进行评估的方法,在满足一定信噪比限制条件下,计算出最佳硬件加速模块参数和转换参数,从而得到基于硬件加速的最优定点算法.同时,在此方法基础上进一步研究了单核SoC芯片内置硬件加速模块的原型开发策略.     

A 15-b pipelined CMOS floating-point A/D converter

A floating-point approach can be used to extend the dynamic range of analog-to-digital (A/D) converters in applications where large signals need not be encoded with a precision greater than that required for small signals. Owing to the nonuniform nature of the quantization in a floating-point A/D converter (FADC), it is possible to sacrifice a large peak signal-to-noise ratio to obtain savings in power dissipation and area while achieving a large dynamic range. A 15-b switched-capacitor pipelined FADC has been designed with a 10-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The increased dynamic range is obtained with a three-stage pipelined variable gain amplifier, while the mantissa is determined by a uniform 10-b pipelined A/D converter. An experimental prototype of the converter has been integrated in a 0.5 μm CMOS technology. It achieves a dynamic range of 90 dB at a conversion rate of 20 MSamples/s with a total power dissipation of 380 mW     

一种面向流量异常检测的概率流抽样方法

针对基于概率抽样的网络流量异常检测数据集构造过程中无法同时兼顾大、小流抽样需求及未区分flash crowd与流量攻击等问题,该文提出一种面向流量异常检测的概率流抽样方法。在对数据流按目的、源IP地址进行分类的基础上,将每类数据流抽样率定义为其目的、源IP地址抽样率的最大值,并在抽样过程中对数据流抽样数目向上取整,保证每类数据流至少被抽样一次,使抽样得到的数据集可有效反映原始流量在大、小流和源、目的IP地址方面的分布性。采用源IP地址熵刻画异常流源IP地址分散度,并基于源IP地址熵阈值设计攻击流抽样算法,降低由flash crowd引起的非攻击异常流抽样概率。仿真结果表明,该方法能同时满足大、小流抽样需求,具有较强的异常流抽样能力,可抽样到所有与异常流相关的可疑源、目的IP地址,并能在抽样过程中过滤非攻击异常流。     

Matlab定点仿真在FPGA验证平台中的应用

无论在雷达系统还是在通信系统当中,对其各种信号处理方法进行仿真时,数据是以浮点形式参与运算,当把算法移植到硬件中实现时,数据是以固定长度的二进制形式参与运算。文中介绍如何利用Matlab定点工具箱实现数据的浮点到定点转换,并结合设计实例,阐明了定点仿真在FPGA验证平台中的应用。实践证明,进行定点仿真是FPGA实现的前提,同时还可以验证FPGA中运算结果的正确性。     

IP Trap的实现与应用研究

IP Trap是用来截获TCP/IP层数据信息的软件,可以把连接发起端和终端的数据信息无修改地保存下来供管理者分析。通过对IP Trap技术及网络互联协议的学习、总结和研究,采用套接字编程,设计出自己的IP Trap软件。软件采用客户/服务器（C/S）模式,实现了IP地址的动态捕获,使服务器端能准确地截获并保存客户端的相关数据,增强网络安全分析的可实施性。