A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

High frequency performance of Si/sub 1-x/Ge/sub x//Si/sub 1-y/Ge/sub y//Si/sub 1-x/Ge/sub x/ HBTs

The results of a theoretical study of the performance of high speed SiGe HBTs is presented. The study includes a group of SiGe HBTs in which the Ge concentration in the base is 20% higher than that in the emitter and collector (i.e. y=x+0.2). It is shown that the composition dependences of f/sub T/ and the F/sub max/ are non-monotonic. As the Ge composition in the emitter and collector layers is increased, f/sub T/ and f/sub max/ first decrease, then remain constant and finally increase to attain their highest values.<>     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

A novel low-voltage N-channel heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) with p-type doped SiGe body

A novel N-channel Si/SiGe heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) has been proposed and fabricated. The Si/SiGe N-HDTMOS consists of an unstrained surface Si channel and heavily p-type doped SiGe body. The potential of the conduction band edge of the surface Si channel can be lowered by introducing a heavily p-type doped SiGe layer into a suitable position in the body region. As a result, the N-HDTMOS shows a threshold voltage reduction and a body effect factor (/spl gamma/) enhancement while keeping high doping concentration in the SiGe layer. The fabricated SiGe N-HDTMOS exhibits superior properties, that is, 0.1 V reduction of V/sub th/, 1.5 times enhancement of /spl gamma/, and 1.3 times saturated current, as compared with those of Si N-DTMOS.     

Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si/sub 1-y/C/sub y/ incorporation

We have demonstrated the fabrication of n/sup +/-p gated diodes using low-temperature annealing of 700/spl deg/C for 30 s with a significantly reduced junction leakage current. This is achieved with the incorporation of an epitaxially grown Si/sub 1-y/C/sub y/(y=0.0007) layer in the substrate located at the end-of-range (EOR) of arsenic implantations. The carbon devices show effectively suppressed EOR defects in the cross-sectional transmission electron microscopy images and leakage characteristics similar to the controlled silicon device fabricated under high-temperature annealing of 950/spl deg/C for 30 s. Arrhenius measurement of the leakage profiles has indicated identical leakage mechanism for both the pure silicon and carbon devices, thus signifying the substantial elimination of the secondary EOR defects resulted from the implantations despite the low-temperature annealing of the latter.     

On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs

The threshold voltage shifts (/spl Delta/V/sub t(SS)/ relative to V/sub t/ of Si-control devices) in strained-Si-Si/sub 1-x/Ge/sub x/ (SS) CMOS devices are carefully examined in terms of the shifted two-dimensional energy subbands and the modified effective conduction- and valance-band densities of states. Increased electron affinity as well as bandgap narrowing in the SS layer are shown to be the predominant components of /spl Delta/V/sub t(SS)/, whereas the density-of-state terms tend to be relatively small but not insignificant. The study reveals, for both n-channel and p-channel SS MOSFETs, important physical insights on the varied surface potential at threshold, defined by energy quantization as well as the strain, and on the shifted flat-band voltage that is also part of /spl Delta/V/sub t(SS)/. Models for /spl Delta/V/sub t(SS)/ dependent on the Ge content (x), with comparisons to published data, are presented and used to show that redesign of channel doping in the SS nMOSFET to increase the significantly reduced V/sub tn(SS)/ for off-state current control tends to substantively diminish the inherent SS CMOS relative speed enhancement, e.g., by more than 40% for x=0.20. Interestingly, the SS pMOSFET model predicts small increases in the magnitude of V/sub tp(SS)/.     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

Effect of band alignment and density of states on the collector current in p-Si/n-Si/sub 1-y/C/sub y//p-Si HBTs

p-Si/n-Si/sub 1-y/C/sub y//p-Si heterojunction bipolar transistors with varying carbon fractions in the base were grown by rapid thermal chemical vapor deposition (RTCVD), to better understand the potential of Si/sub 1-y/C/sub y/ in enhancing the performance of Si-based bipolar technology. The band line-up issues which make Si/sub 1-y/C/sub y/ a desirable choice for forming the base region in a p-n-p HBT are discussed. Electrical measurements performed on the p-Si/n-Si/sub 1-y/C/sub y//p-Si HBTs (y=0.6, 0.8 at.%) are used to extract important information regarding the electronic properties of the Si/Si/sub 1-y/C/sub y/ material system, e.g., the bandgap reduction in Si/sub 1-y/C/sub y/ compared to Si and minority carrier recombination lifetime in Si/sub 1-y/C/sub y/. Temperature dependent measurements of the collector current were performed to extract the bandgap narrowing at the Si/Si/sub 1-y/C/sub y/ heterojunction. This paper includes a detailed analysis of the impact of heavy doping and reduced density of states in Si/sub 1-y/C/sub y/ compared to Si on the extraction of the energy bandgap offset, and on the collector current of p-n-p HBTs. The impact of the reduced density of states on the design of p-n-p Si/Si/sub 1-y/C/sub y/ HBTs is discussed. The measured value of the energy band offset is (65 meV/at.% C) very close to previously measured values of the conduction band offset at the Si/Si/sub 1-y/C/sub y/ heterojunction. The results are thus consistent with a band line-up at the Si/Si/sub 1-y/C/sub y/ interface that is dominated by a conduction band offset with little if any valence band offset.     

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.     

Effect of different type intermediate layers on band structure and gain of Ga/sub 1-x/In/sub x/N/sub y/As/sub 1-y/-GaAs quantum well lasers

Based on the band-anticrossing model, the effect of the strain-compensated layer and the strain-mediated layer on the band structure, the gain, and the differential gain of GaInNAs-GaAs quantum well lasers have been investigated. Different band-filling mechanisms have been illustrated. Compared to the GaInNAs-GaAs single quantum well with the same wavelength, the introduction of the strain-compensated layer and the strain-mediated layer increases the transparency carrier density. However, these multilayer structures help to suppress the degradation of the differential gain.     

A novel high performance SiGe channel heterostructure dynamicthreshold pMOSFET (HDTMOS)

In this letter, we propose a novel SiGe channel heterostructure dynamic threshold metal oxide semiconductor (DTMOS) and demonstrate its superiority over conventional Si-DTMOS. The introduction of a SiGe layer for the channel is very effective for reducing the threshold voltage in spite of keeping impurity doping level at the body region. Therefore, a low threshold voltage and a large body effect factor can be achieved simultaneously. The SiGe HDTMOS with highly doped body exhibits two times higher transconductance, 1.4 times higher saturation current, and better short channel immunity than that of the control Si-DTMOS with lightly doped body of which threshold voltage is nearly the same     

Effect of Mg doping on the superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta//

Superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// (Cu/sub 1-x/Tl/sub x/Mg/sub y/-1234) material have been studied in the composition range y=0,1.5,2.25. The zero resistivity critical temperature [T/sub c/(R=0)] was found to increase with the increased concentration of Mg in the unit cell; for y=1.5 [T/sub c/(R=0)]=131 K was achieved which is hitherto highest in Cu/sub 1-x/Tl/sub x/-based superconductors. The X-ray diffraction analyses have shown the formation of a predominant single phase of Cu/sub 0.5/Tl/sub 0.5/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// superconductor with an inclusion of impurity phase. It is observed from the convex shape of the resistivity versus temperature measurements that our as-prepared material was in the region of carrier over-doping, and the number of carriers was optimized by postannealing experiments in air at 400/spl deg/C, 500/spl deg/C, and 600/spl deg/C. The T/sub c/(R=0) was found to increase with postannealing and the best postannealing temperature was found to be 600/spl deg/C. The mechanism of increased T/sub c/(R=0) is understood by carrying out infrared absorption measurements. It was observed through softening of Cu(2)-O/sub A/-Tl apical oxygen mode that improved interplane coupling was a possible source of enhancement of T/sub c/(R=0) to 131 K.     

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.     

Molecular beam epitaxy of in1-xGaxASyP1-y(y ≃2.2 ×) lattice matched to InP using gas cells

In this paper we report MBE growth of quaternary alloys In_1-xGa_xAs_yP_1-y (y≃2.2x, 0 <y < 1) lattice matched to InP, by using gas cells as sources of V elements. The growth is performed in a MBE system which can receive both gas and solid cells. An efficient pumping system made from association of cryo and turbo molecular pumps allows a background hydrogen pressure of ≃ 10^-5 Torr during the growth. Gas sources produce P₂ and As₂ flux from cracking of PH₃ and AsH₃. An accurate and flexible control of P₂ and As₂ flux is obtained by monitoring the gas cells by a mass selector system. Electron probe analysis and X-ray diffraction show that reproducible growth of homogeneous quaternary layers with a precise control of the composition can be achieved with gas cells. Possible contamination by residual impurities coming from the cracking furnace is investigated by low temperature photoluminescence (8 K). Typical spectrum (8 K) exhibits a narrow near band edge peak (FWHM = 17 meV) and a secondary peak located at 14 meV below the first one which is attributed to carbon acceptor impurity. Room temperature photoluminescence efficiency is equal to that obtained by LPE. For In_0.60Ga_0.40As_0.90Po_0.10 background carrier concentration isn = 10¹⁶cm^-3 with electron mobilities μ (300 K) = 6000 cm²/Vsec and μ (77 K) = 13000 cm²/Vsec.     

A submicrometer 252 GHz f/sub T/ and 283 GHz f/sub MAX/ InP DHBT with reduced C/sub BC/ using selectively implanted buried subcollector (SIBS)

The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic C/sub BC/ of InP-based double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing /spl tau//sub C/, while simultaneously allowing the extrinsic collector to be thick, reducing C/sub BC/. For a 0.35 /spl times/ 6 /spl mu/m/sup 2/ emitter InP-based DHBT with a SIBS, 6 fF total C/sub BC/ and >6 V BV/sub CBO/ were obtained with a 110-nm intrinsic collector thickness. A maximum f/sub T/ of 252 GHz and f/sub MAX/ of 283 GHz were obtained at a V/sub CE/ of 1.6 V and I/sub C/ of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of /spl sim/2.0 and /spl sim/1.4, respectively, at an I/sub C/ of 100 /spl mu/A, and a peak dc /spl beta/ of 36 were measured.     

A novel low-voltage content-addressable-memory (CAM) cell with afast tag-compare capability using partially depleted (PD) SOI CMOSdynamic-threshold (DTMOS) techniques

This paper reports a novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. With two auxiliary pass transistors to dynamically control the bodies of transistors in the tag-compare portion of CAM cell, this SOI CAM cell has a fast tag-compare capability at a low supply voltage of 0.7 V as verified by the results from the two-dimensional semiconductor device simulation program MEDICI     

Electrical characteristics and reliability of UV transparent Si/sub 3/N/sub 4/ metal-insulator-metal (MIM) capacitors

In this paper, we discuss the electrical characteristics and reliability of UV transparent Si/sub 3/N/sub 4/ metal-insulator-metal (MIM) capacitors. We examine film thicknesses in the range of 55 to 25 nm with capacitance densities from 1.2 ff//spl mu/m/sup 2/ to 2.8 ff//spl mu/m/sup 2/, respectively, for single MIM capacitors. A new approach for projecting the dielectric reliability of these films extends the limits of maximum operating voltage. Accounting for temperature acceleration and area scaling, the projected lifetimes can be met for a wide range of operating conditions.     

HgCdTe/CdTe/Si(211)异质结构的应变和应力分布计算

计算了HgCdTe/CdTe/Si(211)异质结构的应变和应力分布,发现对于生长方向为不具有对称特性的[211]晶向,由于弹性模量的各向异性,平行表面的两个晶向方向[1-1-1]和[01-1]的应变和应力分布存在差异,并且二者的曲率半径也具有相应特性。对于Si衬底厚度为500μm,CdTe缓冲层厚度为10μm,HgCdTe层厚度为10μm的异质结构,液氮温度77 K时衬底与外延层的应变均为负值,外延层和衬底的最大应力值均在界面处,外延层中均为张应力,Si衬底在靠近界面处为压应力,远离界面逐渐过渡为张应力,存在一个应力为零的中性轴位置。     

Impedances of an Elliptic Waveguide (For the /sub e/H/sub 1/ Mode) (Correction)

G. R. Valenzuela, author of "Impedances of an Elliptic Waveguide (For the /sub e/H/sub 1/ Mode)," which appeared on pp. 431-435 of the July, 1960, issue of these Transactions, has brought the following to the attention of the Editor.     

A dynamic channel assignment algorithm for a hybrid TDMA/CDMA-TDDinterface using the novel TS-opposing technique

It has been demonstrated that code division multiple access (CDMA) provides great flexibility by enabling efficient multiuser access in a cellular environment. In addition, time division duplex (TDD) as compared to frequency division duplex (FDD) represents an appropriate method to cater for the asymmetric use of a duplex channel. However, the TDD technique is subject to additional interference mechanisms compared to an FDD system, in particular if neighboring cells require different rates of asymmetry. If TDD is combined with an interference limited multiple access technique such as CDMA, the additional interference mechanism represents an important issue. This issue poses the question of whether a CDMA/TDD air-interface can be used in a cellular environment. The problems are eased if a hybrid time division multiple access (TDMA)/CDMA interface (TD-CDMA) is used. The reason for this is that the TDMA component adds another degree of freedom which can be utilized to avoid interference. This, however, requires special channel assignment techniques. A notable example of a system which uses a TD-CDMA/TDD interface is the Universal Mobile Telecommunications System (UMTS). This paper presents a novel centralized dynamic channel assignment (DCA) algorithm for a TD-CDMA/TDD air-interface. The DCA algorithm exploits a new technique which is termed “TS-opposing technique.” The key result is that the new DCA algorithm enables neighboring cells to adopt different rates of asymmetry without a significant capacity loss