A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO

An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6-μm high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm×4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s     

A 622-Mb/s 8×8 ATM switch chip set with shared multibufferarchitecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing     

A 16×622 Mb/s ATM switch: PRELUDE switch architectureintegrated into a 6-million transistor monochip

This paper presents the integration of the Prelude switch architecture into a monochip ATM switch, COM16M, capable of handling 16 multiplexes carrying ATM cells at 622 Mb/s. It is a fully autonomous switch, i.e., the chip includes clock adaptation, routing, and cell buffering as well as header translation and control capabilities. The switch is integrated into one single chip containing 6000000 transistors implemented in a 0.5-μm CMOS process     

A 0.8-μm BiCMOS ATM switch on an 800 Mb/s asynchronous bufferedbanyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8-μm BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical)     

Design and performance of Multinet switch: a multistage ATM switcharchitecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches     

An approximate analysis of shared‐buffer channel‐grouped ATM switches under imbalanced traffic

Grouping output channels in a shared‐buffer ATM switch has shown to provide great saving in buffer space and better throughput under uniform traffic. However, uniform traffic does not represent a realistic view of traffic patterns in real systems. In this paper, we extend the queuing analysis of shared‐buffer channel‐grouped (SBCG) ATM switches under imbalanced traffic, as it better represent real‐life situations. The study focuses on the impact of the grouping factor and other key switch design parameters on the performance of such switches as compared to the unichannel allocation scheme in terms of cell loss probability, throughput, mean cell delay and buffer occupancy. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is presented. Copyright © 2005 John Wiley & Sons, Ltd.     

A high-speed CMOS circuit for 1.2-Gb/s 16*16 ATM switching

The authors describe a 0.7- mu m CMOS asynchronous transfer mode (ATM) switch circuit of 350 K transistors, the kernel of a fully autonomous 16*16 ATM switching matrix devoted to telecommunications. This matrix is able to switch ATM multiplexes with a throughput of up to 1.2 Gb/s per access line, and was implemented using 16 receiver/transmitter circuits and a control circuit. The architecture of the ATM switch circuit is based on a large embedded and shared dual-access memory. Each chip processes 4-b slices of each incoming multiplex. Seven such chips working in parallel are enough to achieve standard ATM cell switching. Up-to-date test features, such as boundary scan, built-in self-test, and redundancy were implemented in the circuit.<>     

A recursive modular terabit/second ATM switch

The author proposes a recursive modular architecture for a very large scale asynchronous transfer mode (ATM) switch. By extending the concept of the original knockout switch, the cell filtering and contention resolution functions are distributed over many small switch elements, which are arranged in a crossbar structure. The output ports of a switch fabric are partitioned into a number of groups by a novel grouping network to permit sharing of the routing paths in the same group. This partitioning and sharing concept is applied recursively to construct the entire switch elements. The technique of channel grouping for trunk circuits can be incorporated in the proposed ATM switch to improve the cell loss/delay performance while the cells' sequences are retained. A prototype circuit for the key switch element has been designed, and it has been shown that more than 4000 of the switch elements can be integrated into a VLSI chip with existing CMOS 1-μm technology     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

Scalable shared-buffering ATM switch with a versatile searchablequeue

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 μm CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32×8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 μm pure CMOS technology. By using four chip sets, a 622 Mbit/s 32×32 switch can be installed on one board     

Realization of large capacity ATM switches

Large-capacity ATM switches, with switching capacity in excess of 40 Gb/s or 100 Gb/s, are becoming an essential part of network growth. To realize such switches requires technology know-how as well as implementation trade-off considerations. This article provides a system-level exploration of large-capacity ATM switches in terms of switch fabric scalability, cell buffer management, buffer design trade-off, call processing capabilities, and future trends in switch design     

Accurate modelling of the queueing behaviour of shared buffer ATM switches

A model for the analysis of multistage switches based on shared buffer switching for Asynchronous Transfer Mode (ATM) networks is developed, and the results are compared with the simulation. Switches constructed from shared buffer switches do not suffer from the head of line blocking which is the common problem in simple input buffering. The analysis models the state of the entire switch and extends the model introduced by Turner to global flow control with backpressure mechanism. It is shown that buffer utilization is better and throughput improves significantly compared with the same switch using local flow control policy. Copyright © 1999 John Wiley & Sons, Ltd.     

A 100-Gb/s throughput ATM switch MCM with a 320-channel paralleloptical I/O interface

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-μm complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface     

Queuing analysis of shared‐buffer ATM switches with grouped output channels

Shared buffering and channel grouping are powerful techniques with great benefits in terms of both performance and implementation. Shared‐buffer switches are known to have better performance and better utilization than input or output queued switches. With channel grouping, a cell is routed to a group of channels instead of a specific output channel. In this way, congestion due to output contention can be minimized and the switch performance can therefore be greatly improved. Although each technique is well known by itself in the traditional study of queuing systems, their combined use in ATM networks has not been much explored previously. In this paper, we develop an analytical model for a shared‐buffer ATM switch with grouped output channels. The model is then used to study the switch performance in terms of cell loss probability, cell delay and throughput. In particular, we study the impact of the channel grouping factor on the buffer requirements. Our results show that grouping the output channels in a shared‐buffer ATM switch leads to considerable savings in buffer space. Copyright © 2001 John Wiley & Sons, Ltd.     

32×32 shared buffer type ATM switch VLSIs for B-ISDNs

A set of 0.8 μm CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32×32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32×32 switching board to achieve large-scale switching systems such as 256×256 or 1024×1024 switches are discussed     

NN based ATM cell scheduling with queue length-based priorityscheme

The asynchronous transfer mode (ATM) is the choice of transport mode for broadband integrated service digital networks (B-ISDNs). We propose a window-based contention resolution algorithm to achieve higher throughput for nonblocking switches in ATM environments. In a nonblocking switch with input queues, significant loss of throughput can occur due to head-of-line (HOL) blocking when first-in first-out (FIFO) queueing is employed. To resolve this problem, we employ bypass queueing and present a cell scheduling algorithm which maximizes the switch throughput. We also employ a queue length based priority scheme to reduce the cell delay variations and cell loss probabilities. With the employed priority scheme, the variance of cell delay is also significantly reduced under nonuniform traffic, resulting in lower cell loss rates (CLRs) at a given buffer size. As the cell scheduling controller, we propose a neural network (NN) model which uses a high degree of parallelism. Due to higher switch throughput achieved with our cell scheduling, the cell loss probabilities and the buffer sizes necessary to guarantee a given CLR become smaller than those of other approaches based on sequential input window scheduling or output queueing     

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

A Shared Buffer Memory ATM Access Switch

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A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

A 250-Mb/s 32×32 CMOS crosspoint LSI for ATM switchingsystems

A 32×32 crosspoint LSI and a time-slot controlled asynchronous-transfer-mode (ATM) switch architecture utilizing the LSI are presented. The ATM switch, which is classified as an input-buffer-type ATM switch, enables 99% throughput and broadcasting capability. The crosspoint LSI is characterized by the bit-map oriented and pipelined connection control method which can switch and broadcast 160-Mb/s ATM cells, 32×32 switch cells which have less parasitic capacitance, and emitter-coupled-logic (ECL) compatible interfaces which are compatible with a 160-MHz broadband ISDN data rate. The LSI has been fabricated by a 1-μm CMOS process. The chip size is 7.4 mm×7.4 mm. According to the evaluation, operation at 250 Mb/s is confirmed. 1.2-W power consumption is observed at 160-Mb/s operating condition