共查询到20条相似文献,搜索用时 31 毫秒
1.
A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 106 for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications 相似文献
2.
《Electron Devices, IEEE Transactions on》1998,45(3):701-709
Low-energy ion implantation is investigated in detail as a method of fabricating ultrashallow and low resistance source/drain (S/D) extensions for 0.15-μm MOSFETs. High-temperature rapid thermal annealing (RTA) is found to be essential for obtaining a shallow junction with low sheet resistance. Significant degradation of carrier activation efficiency and a serious increase in sheet resistance were observed when the acceleration energy was lowered to 10 keV. Only 10% of the implanted atoms were activated by either 1-keV BF2or As-implantation. Both p- and n-MOSFETs were fabricated using low-energy (10-20 keV) BF2- and As-implantation with RTA. The p- and n-MOSFETs with a 0.15-μm gate length showed adequate short-channel characteristics, but their drive current was too low. The analysis of the S/D parasitic resistance shows that the low current drivability is due to the increase in the S/D sheet resistance of extensions for a p-MOSFET and the S/D edge resistance under the gate electrode for an n-MOSFET 相似文献
3.
S. Theodore Chandr N. B. Balamurugan G. Subalakshmi T. Shalini G. Lakshmi Priya 《半导体学报》2014,35(11):114003-5
We have developed a 2D analytical model for the single gate Al In Sb/In Sb HEMT device by solving the Poisson equation using the parabolic approximation method.The developed model analyses the device performance by calculating the parameters such as surface potential,electric field distribution and drain current.The high mobility of the Al In Sb/In Sb quantum makes this HEMT ideal for high frequency,high power applications.The working of the single gate Al In Sb/In Sb HEMT device is studied by considering the variation of gate source voltage,drain source voltage,and channel length under the gate region and temperature.The carrier transport efficiency is improved by uniform electric field along the channel and the peak values near the source and drain regions.The results from the analytical model are compared with that of numerical simulations(TCAD) and a good agreement between them is achieved. 相似文献
4.
Dun-Nian Yaung Shou-Gwo Wuu Yean-Kuen Fang Wang C.S. Chien-Hsien Tseng Mon-Song Lian 《Electron Device Letters, IEEE》2001,22(2):71-73
A nonsilicide source/drain pixel is proposed for high performance 0.25-μm CMOS image sensor. By using organic material spin coat and etch back, silicide is only formed on poly gate which can be used as interconnection, not for source/drain region that solve the optical opaqueness and undesirably large junction leakage of silicide. The performance of MOSFET changes little due to the high sheet resistance of nonsilicide source/drain. With H2 annealing and double ion implanted source/drain junction, the dark current can be further reduced. The novel pixel (three transistors, 3.3 μm×3.3 μm, fill factor: 28%) shows low dark current (less than 0.5 fA per pixel at 25°C) and high photoresponse 相似文献
5.
《Solid-State Circuits, IEEE Journal of》1976,11(4):472-477
A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor. 相似文献
6.
Jang-Gn Yun Soon-Young Oh Bin-Feng Huang Hee-Hwan Ji Yong-Goo Kim Seong-Hyung Park Heui-Seung Lee Dae-Byung Kim Ui-Sik Kim Han-Seob Cha Sang-Bum Hu Jeong-Gun Lee Sung-Kweon Baek Hyun-Sang Hwang Hi-Deok Lee 《Electron Device Letters, IEEE》2005,26(2):90-92
In this letter, hydrogen plasma immersion ion implantation (H PIII) with Ni-Co-TiN tri-layer is introduced for the first time to enhance the thermal stability of the Ni-silicide for nanoscale CMOS technology. The Ni-silicided poly-Si gate and source/drain showed stable sheet resistance in spite of 650/spl deg/C, 30 min post-silicidation annealing. The junction leakage current is even improved a lot without degradation of device performance using the proposed method. 相似文献
7.
Il-Suk Kang Shin-Hee Han Seung-Ki Joo 《Electron Device Letters, IEEE》2008,29(3):232-234
We propose an offset-gated bottom gate polycrystalline silicon thin-film transistor (TFT), with a combination structure of ultrathin channel and raised source/drain, employing a simple process of the back surface exposure. It is experimentally and simulatively demonstrated that the new device has lower leakage current and better saturation characteristics, as compared with the conventional non offset TFT, due to the lateral electric field near the drain, which is reduced by the proposed structure. Moreover, the proposed TFT exhibits much better ON/OFF current ratio because the high current drive due to the raised source/drain structure is enough to compensate for the ON-state current reduction due to the offset-gate structure. 相似文献
8.
《Electron Devices, IEEE Transactions on》2009,56(8):1618-1623
9.
A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is proposed and experimentally demonstrated. The unique feature of the technology is the formation of self-aligned and symmetrical lightly doped source/drain (LDD) structure without any additional photolithographic or implantation steps. Thus, the number of masks used in the technology is the same as that in a conventional top gate TFT technology. Moreover, devices formed by the proposed method have thick source/drain and a thin channel region for providing low source/drain resistance and improved I-V characteristics. P-channel TFT devices are fabricated using a simple low temperature (⩽600°C) process. The fabricated SABG-TFT exhibits symmetrical transfer characteristics when the polarity of source/drain bias is reversed. The effective mobility and on-off current ratio of the devices are about 35 cm2/V-s and 6×106 respectively 相似文献
10.
Chen C.L. Mahoney L.J. Nichols K.B. Manfra M.J. Gramstorff B.F. Molvar K.M. Murphy R.A. Brown E.R. 《Electron Device Letters, IEEE》1995,16(5):199-201
GaAs MISFET's with a low-temperature-grown (LTG) GaAs gate insulator and ion-implanted self-aligned source and drain n+ regions are demonstrated. The resistivity and breakdown field of the LTG GaAs insulator were not changed appreciably by implantation and 800°C activation annealing. The gate leakage current remained very low at a value of approximately 1 μA per μm2 of gate area at 3 V forward gate bias. Because of the reduced source and drain resistance, the drain saturation current and the transconductance of self-aligned MISFET's increased more than twofold after ion implantation 相似文献
11.
Ren F. Kuo J.M. Hong M. Hobson W.S. Lothian J.R. Lin J. Tsai H.S. Mannaerts J.P. Kwo J. Chu S.N.G. Chen Y.K. Cho A.Y. 《Electron Device Letters, IEEE》1998,19(8):309-311
We have demonstrated the first Ga2O3(Gd2O3) insulated gate n-channel enhancement-mode In0.53Ga0.47As MOSFET's on InP semi-insulating substrate. Ga2O3(Gd2 O3) was electron beam deposited from a high purity single crystal Ga5Gd3O12 source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, ft, and the maximum frequency of oscillation, fmax, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm2 gate dimension device at a gate voltage of 3 V and drain voltage of 2 V 相似文献
12.
Remarkable Reduction of On-Resistance by Ion Implantation in GaN/AlGaN/GaN HEMTs With Low Gate Leakage Current 总被引:1,自引:0,他引:1
Nomoto K. Tajima T. Mishima T. Satoh M. Nakamura T. 《Electron Device Letters, IEEE》2007,28(11):939-941
We demonstrate Si ion-implanted GaN/AlGaN/GaN high-electron mobility transistors with extremely low gate leakage current and low source resistance without any recess etching process. The source/drain (S/D) regions were formed using Si ion implantation into undoped GaN/AlGaN/GaN on sapphire substrate. Using ion implantation into S/D regions with an energy of 80 keV, the performances were significantly improved. On-resistance decreased from 26.2 to 4.3 Omegaldrmm. Saturation drain current and maximum transconductance increased from 284 to 723 mA/mm and from 48 to 147 mS/mm. 相似文献
13.
Jun Cai Harley-Stead M. Park S. Woloszyn J. Gallacher V. 《Electron Device Letters, IEEE》2005,26(7):495-497
A novel high-voltage MOSFET structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain (S/D) is proposed. The asymmetric hetero-doped S/D reduces the on-state resistance of the transistor due to the high doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n/sup +/ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped S/D structure allows the high voltage MOSFET to have a high current handling capability with a small device size. This in turn causes the R (sp, on) to be low, leading to high performance for the power device when used in a power integrated circuit. Measured results show that a 24-V breakdown voltage new device with a low-cost two-layer metal (Al) back-end achieves very low R (sp, on) of 0.166 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the new device with a 65-V high-side capability achieves good isolation performance even when switching S/D to -20 V and also gets a cutoff frequency of 13 GHz at a gate voltage of 5.5 V. 相似文献
14.
15.
The development of a complete complementary MESFET technology is presented. The state-of-the-art, fully implanted, CMOS-like process uses Shannon implants together with a refractory silicide Schottky-gate material to combine high gate barrier heights with ease of fabrication. To minimize parasitic resistances, a unique sidewall structure and sidewall spacers are utilized to allow for self-aligned implantation of the source/drain regions. A self-aligned titanium silicidation technique is employed to minimize sheet and contact resistance of the source/drain regions. The SUPREM process simulator was employed extensively. The performance and modeling of device parameters (e.g., threshold voltage, gate leakage, and short-channel effects) and circuit parameters (e.g. standby current, noise margin, and speed) were accomplished through analytic formulations, the PISCES two-dimensional device simulator, and the SPICE circuit simulator 相似文献
16.
Bhagwan Ram Raad Dheeraj Sharma Pravin Kondekar Kaushal Nigam Sagar Baronia 《International Journal of Electronics》2013,100(12):1992-2006
We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n+ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated. 相似文献
17.
《Electron Device Letters, IEEE》1986,7(1):16-19
An asymmetrical drain, substrate, and gate current phenomenon with respect to drain-source reversal in short-channel lightly doped-drain (LDD) and minimum-overlap MOSFET has been observed. By controlled device fabrication splits, it is confirmed that these asymmetrical device characteristics are caused by the 7° off-axis drain-source implant which creates different degrees of offset between the gate edge and the source-drain junctions. The offset degrades the I-V characteristics. Substrate and gate current asymmetries are studied by analyzing the channel electrical field using two-dimensional device simulations. High-channel field at the source end is proposed to explain the second hump in the double-humped substrate current characteristic and the strong gate current injection when the devices are operated with the nonoverlap side as the source. One way to avoid the shadowing effect at ion implantation is to etch the poly-gate side wall to a small positive level angle. 相似文献
18.
Mogami T. Wakabayashi H. Saito Y. Tatsumi T. Matsuki T. Kunio T. 《Electron Devices, IEEE Transactions on》1996,43(6):932-939
A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi2 on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi2 films were achieved on all narrow, long n+ and p+ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi2 films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n+ and p+ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi2 films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi2 films 相似文献
19.
许淼 殷华湘 朱慧珑 马小龙 徐唯佳 张永奎 赵治国 罗军 杨红 李春龙 孟令款 洪培真 项金娟 高建峰 徐强 熊文娟 王大海 李俊峰 赵超 陈大鹏 杨士宁 叶甜春 《半导体学报》2015,36(4):044007-4
文章研究了亚 20nm 节点后栅工艺体硅 FinFET PMOS 器件制作过程中一系列工艺参数对器件微缩的影响。实验结果表明细且陡的梯形Fin结构有更好的性能。文章针对穿通阻挡层(PTSL) 和轻掺杂源漏扩散区 (SDE)的注入条件也进行了仔细地优化。SDE之后没有热退火过程的器件由于在源漏退火之后有更好的晶格再生因而拥有更大的驱动电流。带边功函数器件能够改善短沟道效应,而带中功函数具有更大的驱动电流。器件在微缩过程中针对金属栅的有效功函数需要折衷选择。 相似文献
20.
E.F. Stikvoort 《Solid-state electronics》1979,22(6):595-598
A new device for mixing in the VHF range is presented which has very low third-order distortion. The device consists of a DMOST having a polysilicon resistive gate which is biased by a d.c. current that flows at right angles to the source to drain current in the DMOST. As a result of this gate bias current the device has a drain current to input gate voltage characteristic with a large square low region when the drain operates above the “pinch off” voltage. Samples of the device exhibit an extremely quadratic behaviour over several volts of the input gate voltage. 相似文献