一种用于无线植入式神经控制信号传输的低功耗BPSK解调器的CMOS实现

本文提出了一种新的BPSK解调器。在这个解调器中,设计了一种结构非常简单的时钟倍频器电路来代替传统BPSK解调器中的模拟乘法器,使得所设计的解调器电路结构简单、功耗较低,从而更适合于无线植入式神经记录系统中体内部分的单芯片设计。所提出的BPSK解调器采用Global Foundries 0.35 ?m 3.3 V标准CMOS工艺实现,芯片面积仅0.07 mm2,功耗只有0.5 mW。芯片测试结果证明它能正常工作。     

A low-power RF integrated circuit for implantable sensors

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 μW of power, which is therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 μm bulk CMOS technology. Experimental results show good agreement with the simulation results.     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

低功耗输出脉冲幅度和频谱可调的超宽带发送机设计

A 3-5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2 × 1.4 mm^2.     

A fully integrated BPSK amplitude and spectrum tunable transmitter for IR-UWB system

A 3-5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13 μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2×1.4 mm2.     

Successive-divider-line ADC dedicated to low-power medical devices

A low-power and small silicon area digitally controlled Switched Mode Power Supply (SMPS) is intended for the minimization of both power and size of an on-chip DC power supply building block which is mainly dedicated for implantable medical sensing and microstimulation devices. Such SMPS is based on a successive divider-line analog-to-digital Converter (SDLADC), which is the focus of this paper. Special attention is paid for reducing the power consumption and silicon area of this SDLADC, which consists of a resistor network based on diode connected transistor used to replace the delay-line of the windowed ADC. To compensate process and temperature variations, a digital calibration technique is used to meet the specified static and dynamic output voltage regulations and avoid variations of the regulated SMPS output voltage. The proposed ADC is implemented in AMS 0.35 μm CMOS process. Simulation results show a current consumption of 1.5 μA/MHz and conversion time of 10 ns much lower than recent conventional topology values. The proposed circuit exhibits a quantization steps smaller than 1.6% of V_ref and it can be a solution for high switching frequency, which results on faster regulation of SMPS output voltage.     

一种适用于UHF频段无源RFID应用的低功耗电源恢复和OOK解调技术

本文提出一种与普通CMOS工艺兼容的、适用于UHF频段无源RFID应用的低功耗电源恢复电路和一种新型OOK解调技术.该解调技术具有结构简单、功耗低、易于集成、适应大动态范围等特点.芯片采用0.18μm CMOS工艺进行设计,测试结果表明在电源电路负载为510kΩ时,恢复出的芯片电源电压为1.6V～2.0V;在发射功率为4WEIRP的条件下,可以在3.7m的距离下正常工作.     

Fully digital BPSK demodulator for satellite supressed carrier telecommand system

In this paper, we present the design of a fully digital binary phase shift keying demodulator for application in satellite high‐rate suppressed carrier telecommand system. The proposed system digitalizes the received signal in the intermediate frequency stage using bandpass sampling technique, and the resulting baseband signal is used to synchronization of symbol and phase and to bit detection. The design of all functional modules is presented in details. Another innovation presented in this work is the inclusion of a non‐linearity in the phase synchronizer module to permit its operation independent from the signal amplitude. Moreover, aiming the characterization and performance evaluation of the system, we do some original mathematical analyses. Finally, test results show that the demodulator complies all the project requirements, and the prototype implementation loss, in terms of bit energy to noise power density ratio, is less than 0.3 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

A fully integrated dual-channel log-domain programmable preamplifier and filter for an implantable cardiac pacemaker

A programmable-gain preamplifier and filter for detection of spontaneous heart activity in an implantable cardiac pacemaker is presented. The system is fully integrated in a standard 0.35-/spl mu/m CMOS technology, including all auxiliary circuits. Two channels are available in order to process both atrial and ventricular signals. CMOS translinear circuits, with particular emphasis on log-domain techniques, have been exploited in order to contain current consumption and to allow correct operation with a reduced supply voltage, due to battery discharging. Indeed, the realized system can operate down to 1.8 V of supply voltage and dissipates at most 1.8 /spl mu/A, granting at least 47 dB of dynamic range (DR) for the atrial chain, which is compatible with advanced digital sensing. Current consumption can be further reduced at the expense of DR if a simpler sensing like peak detection is adopted. All system performance have been verified by measurements results and are compatible with the requirements of cardiac pacemakers. This work, therefore, demonstrates how a proper design approach, exploiting low-power and low-voltage techniques, allows one to optimize performance for the cardiac pacemaker.     

Compact broadband stacked implantable antenna for biotelemetry with medical devices

A compact stacked implantable antenna for biotelemetry in medical implant communication services band (MICS band: 402-405 MHz) is proposed. Using a stacked planar inverted-F antenna (PIFA) structure can enhance bandwidth and reduce the effect of frequency shift in human tissue giving complex and highly variable characteristics. The antenna looks like one dime (US currency) and has a 7.5 mm radius, 1.9 mm thickness, operating frequency at 402 MHz and a bandwidth of 50 MHz at return loss of 10 dB. A miniature, broadband stacked implantable antenna for biotelemetry with medical devices is provided     

一种应用于WIA-PA收发机的低功耗高灵敏度CMOS GFSK解调器

本文针对工业无线传感网WIA-PA标准设计出一款应用于收发机中的低功耗、高灵敏度、频率偏差能够自动消除的GFSK解调器。从低功耗角度出发,该收发机中的接收机采用中频为1.5M的低中频结构,发射机采用基于sigmadelta结构的锁相环间接调制方式。本文提出的GFSK解调器采用TSMC 0.18 um 1P6MRF工艺流片,有效面积为0.14mm2。经测试,该解调器能够处理±180 KHz的频率偏差并没有谐波干扰;在1‰的误码率条件下,仅需要18.5dB的信噪比;并且在1.8V电源供电情况下,整个解调器消耗功耗不超过0.26mA。     

A fully integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers

This work presents an input stage for a cardiac pacemaker fully integrated in 0.35-/spl mu/m CMOS technology. The system can acquire and digitize to 8 bits both atrial and ventricular electrical activity. Log-domain circuits are exploited to amplify and filter the input signal, while /spl Sigma//spl Delta/ modulation is exploited to convert it. The design is power optimized, indeed the current consumption is limited to 2.9 /spl mu/A, while the power supply ranges from 2.8 to 1.8 V. The total area is 2.2 mm/sup 2/ and experimental data prove correct filtering and a total dynamic range of at least 47 dB.     

A low-power precomputation-based fully parallel content-addressable memory

This paper presents a novel VLSI architecture for a fully parallel precomputation-based content-addressable memory (PB-CAM) with low-power, low-cost, and low-voltage features. This design is based on a precomputation approach that saves not only power consumption of the CAM system, but also reduces transistor count and operating voltage of the CAM cell. In addition, the proposed PB-CAM word structure adopts the static pseudo-nMOS circuit design to improve system performance. The whole design was fabricated with the TSMC 0.35-/spl mu/m single-poly quadruple-metal CMOS process. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with power consumption of 33 mW at 3.3-V supply voltage and works up to 30 MHz under 1.5-V supply voltage.     

A low-power integrated circuit for remote speech recognition

In this paper, a low-power, low-voltage speech processing system is presented. The system is intended to he used in remote speech recognition applications where feature extraction is performed on terminal and high-complexity recognition tasks and moved to a remote server accessed through a radio link. The proposed system is based on a CMOS feature extraction chip for speech recognition that computes 15 cepstrum parameters, each 8 ms, and dissipates 30 μW at 0.9-V supply. Single-cell battery operation is achieved. Processing relies on a novel feature extraction algorithm using 1-bit A/D conversion of the input speech signal. The chip has been implemented as a gate array in a standard 0.5-μm, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpus is 10 μJ. It achieves recognition rates over 98% in isolated-word speech recognition tasks     

Wireless switch for implantable medical devices based on passive RF receiver

A wireless switch designated for battery-supplied implantable medical devices is designed and verified based on a passive RF receiver. The switch employs wireless energy recovery and wireless identification, and consumes zero standby power. Unlike the commonly used dry reed switch, the proposed switch features high tolerance to noise and disturbance, as well as compatibility with integrated circuits. The proposed wireless switch circuit has been implemented using 0.18 mm CMOS technology, and verified in a wireless capsule endoscope prototype system.     

A low-power integrated tuner for cable telephony applications

This paper describes an integrated tuner for cable telephony in a 0.35 /spl mu/m, 27 GHz SOI BiCMOS technology. The IC integrates a complete dual-conversion signal path including upconverter, downconverter, variable-gain amplifier, LO synthesizers with fully integrated voltage-controlled oscillators, gain control circuitry, as well as digital calibration and interface circuits. It accepts signals in the 200-880 MHz band and produces a 44 MHz IF. Drawing 168 mA from a 3 V supply, the tuner system has a worst case noise factor of 7.3 dB, system phase noise below -78 dBc/Hz at a 10 kHz offset, spurs below -42 dBc for 137 5 dBmV input channels, a gain of 60 dB, and gain control range of 68 dB. The 13 mm/sup 2/ IC meets specifications across an outdoor temperature range of -40/spl deg/C to 100/spl deg/C in production lots.     

A design for high-speed low-power CMOS fully parallelcontent-addressable memory macros

Described is a design for high-speed low-power-consumption fully parallel content-addressable memory (CAM) macros for CMOS ASIC applications. The design supports configurations ranging from 64 words by 8 bits to 2048 words by 64 bits and achieves around 7.5-ns search access times in CAM macros on a 0.35-μm 3.3-V standard CMOS ASIC technology. A new CAM cell with a pMOS match-line driver reduces search rush current and power consumption, allowing a NOR-type match-line structure suitable for high-speed search operations. It is also shown that the CAM cell has other advantages that lead to a simple high-speed current-saving architecture. A small signal on the match line is detected by a single-ended sense amplifier which has both high-speed and low-power characteristics and a latch function. The same type of sense amplifier is used for a fast read operation, realizing 5-ns access time under typical conditions. For further current savings in search operations, the precharging of the match line is controlled based on the valid bit status. Also, a dual bit switch with optimized size and control reduces the current. CAM macros of 256×54 configuration on test chips showed 7.3-ns search access time with a power-performance metric of 131 fJ/bit/search under typical conditions