Polar SiGe Class E and F Amplifiers Using Switch-Mode Supply Modulation

Two integrated polar supply-modulated class E and F power amplifiers (PAs) in 0.18-mum SiGe BiCMOS process are presented. The amplifiers are used to transmit GSM-EDGE signals with an envelope dynamic range of 11 dB and a frequency range of 880-915 MHz. The amplifiers use switch-mode dc-dc buck converters for supply modulation, where sigma-delta (SigmaDeltaM), delta (DeltaM), and pulsewidth modulation are used to modulate the PA amplitude signal. A framework has been developed for comparing the three switching techniques for EDGE implementation. The measurement results show that DeltaM gives the highest efficiency and lowest adjacent channel power, providing class E and F PA efficiencies of 33% and 31%, respectively, at maximum EDGE output power. The corresponding class E and F linearized amplifiers' output spectra at 400-kHz offset are -54 and -57dBc, respectively     

High Average-Efficiency Multimode RF Transmitter Using a Hybrid Quadrature Polar Modulator

This paper presents a hybrid quadrature polar modulator (HQPM) to drive the power amplifier (PA) highly efficiently in a wireless RF transmitter required for multimode operation. For enhancing the transmit efficiency, a switching-mode PA realized as Class-E design is used in the transmitter. The HQPM consists of a quadrature modulator for processing the RF modulated carrier and a Class-S modulator for processing the supply-voltage signal. The quadrature modulator and the Class-S modulator deliver the output signals with proportional envelope variation before being inserted into the RF-input terminal and the supply-voltage terminal of a Class-E PA, respectively, causing the double envelope modulation to distort the modulated RF signal at the PA output. Therefore, a digital predistorter is embedded in the HQPM for compensation. The proposed HQPM-based transmitter can help reducing the average dc and input RF powers and the output feedthrough levels so as to enhance power added efficiency and adjacent channel power rejection remarkably.     

A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth

This paper presents a CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency when amplifying signals with high linearity requirements. The power amplifier comprises 64 parallel RF amplifiers that are driven by a constant envelope RF phase-modulated signal. The unit amplifiers are digitally activated by a 6-bit envelope code to construct a non-constant envelope RF output, thereby performing a digital-to-RF conversion. In order to suppress the spectral images resulting from the discrete-time to continuous-time conversion of the envelope, the use of oversampling and four-fold linear interpolation is explored. An experimental prototype of the polar amplifier has been integrated in a 0.18- mum CMOS technology, occupies a total die area of 1.8 mm² , operates at a 1.6-GHz carrier frequency with a channel bandwidth of 20 MHz. For an OFDM signal, it achieves a power-added efficiency of 6.7% with an EVM of - 26.8 dB while delivering 13.6 dBm of linear output power and drawing 145 mA from a 1.7-V supply.     

A fast Modulator for dynamic supply linear RF power amplifier

A fast modulator for a dynamic supply linear RF amplifier has been integrated in a 0.35-/spl mu/m CMOS technology. The use of this modulator with an external linear power amplifier (PA) allows to maintain its efficiency at a higher level than it would with the same PA supplied at constant voltage. The modulator is designed to follow rapid envelope variations at high efficiency without compromising the RF PA linearity.     

An All-Digital RF Signal Generator Using High-Speed $DeltaSigma$ Modulators

An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. By adjusting the sample rate, carriers from 50 MHz to 1 GHz can be synthesized. RF signals up to 3 GHz can be synthesized when using the first image band. As an example, UMTS standard can be addressed by using a 2.6 GHz clock frequency. The measured ACPR is then 44 dB for a 5 MHz WCDMA channel at 1.95 GHz with output power of -16 dBm and 3.4% EVM. At 4 GHz clock frequency the total power consumption is 120 mW (49 mW for DeltaSigma modulator core) on a 1 V supply voltage, total die area is 3.2 mm² (0.15 mm² for the active area).     

A LINC-based polar transmitter with reduced envelope bandwidth for wideband communications

This paper presents a polar transmitter with reduced envelope bandwidth and the linear amplifier with nonlinear components (LINC) technique is used to produce constant-envelope signals according to the remaining envelope information. This architecture relaxes the bandwidth requirement for the traditional envelope modulators. Only the low-frequency part of the envelope signal is amplified to provide power supply for the power amplifier (PA) stage. In the LINC path, the remaining envelope information is modulated into the phase signals, which are used as the radio frequency (RF) input to the nonlinear PA pair. At the RF output, the envelope information is retrieved from these two parts by the supply-modulated PA pair. The simulation results show that the envelope bandwidth is reduced to around one third of the original bandwidth by the proposed technique. For 2-level LINC structures, the combining efficiency of the proposed architecture is improved to more than twice as the one of LINC-only structure since the combining angles are reduced.     

A Two-Point Modulation Technique for CMOS Power Amplifier in Polar Transmitter Architecture

A two-point modulation technique is presented that improves the performance of nonlinear power amplifiers (PAs) in polar transmitters. In this scheme, the output amplitude modulation is performed by controlling the current of the PA. The current control technique enables the PA to provide wideband amplitude modulation, as well as high power control dynamic range. In addition, the supply voltage of the PA is adjusted based on the output power level. The voltage supply adjustment substantially improves the effective power efficiency of the PA. The voltage supply control is performed using a second-order sigma-delta dc-dc converter, which presents an efficiency of over 95% in its operational range. The PA operates at 900 MHz with maximum output power of 27.8 dBm and power efficiency of 34% at maximum output power. The proposed PA achieves 62-dB power control dynamic range with amplitude modulation bandwidth of over 17.1 MHz. The circuits are fabricated in a CMOS 0.18 mum process with a 3.3-V power supply.     

包络跟踪的J 类功率放大器设计

为了提高功率放大器的回退效率以更好地适应第五代移动通信系统的高峰均比信号的需求,文中提出 了一种基于包络跟踪的J 类功率放大器的设计方法,通过对电源调制器的设计来动态调制J 类功率放大器的供电电 压,以降低漏极直流功耗,实现提高功率放大器效率的目标。最终的测试结果表明在3.4~3.6 GHz 频率范围内,当采 用带宽20 MHz、峰均比为8.6 dB 的正交频分复用(Orthogonal Frequency Division Multiplexing, OFDM)调制信号时,测得 恒压供电时的功率放大器的回退效率为25.3%~29%;然后采用带宽20 MHz、峰均比为6.4 dB 的64 正交调幅(Quadrature Amplitude Modulation, QAM)调制信号时,测得恒压供电时的功率放大器的回退效率为33.1%~34.1%。而采用包 络跟踪动态供电时所测得的回退效率分别为30.2%~35.1%和37.1%~41.3%,回退效率提升5%~7%。经过数字预失 真处理之后,该功率放大器的邻近信道功率泄露比低于-46dBc,具有良好的线性度。     

A Transmitter Architecture Based on Delta–Sigma Modulation and Switch-Mode Power Amplification

This brief presents a method of deploying RF switch-mode power amplification for varying envelope signals. Thereby the power amplifier can be operated as a switch with a high power efficiency as the result. The key idea is to transmit either a full RF period or none at all in such a way that the correct modulated RF signal is obtained after filtering. This is accomplished in a novel configuration of a low-pass DeltaSigma modulator using a phase modulated clock combined with a simple AND-gate. The designed modulator is easy to implement, displays very good linearity and offers time domain signals that promote the power efficiency of the power amplifier. The working principle is described through theory and simulations, and validation is done via measurements on a prototype of the modulator. Measurements on the prototype show that the presented modulator modulates a UMTS signal with more than 10-dB margin to the spectrum mask and EVM below 0.85% RMS (req<17.5%). Delta-sigma, power amplifier (PA), RF, switch mode, transmitter architecture, varying envelope.     

A low voltage W-CDMA polar transmitter with digital envelope path gain compensation

This letter presents a polar transmitter using a dual-phase pulsewidth-modulated buck converter with a 50-MHz effective switching frequency. Using a wideband code division multiple access voice signal, the overall system can achieve 52.8% drain efficiency (49.8% power added efficiency) at 24-dBm output power at 836.5MHz with a 3.5-V supply voltage, while passing both adjacent channel leakage power ratio (ACLR1) and alternate channel leakage power (ACLR2) specifications. A digital finite impulse response filter is included in the envelope path to compensate for gain roll-off at higher baseband frequencies. This envelope path compensation allows greater linear bandwidth to be achieved at lower switching frequencies, thus boosting efficiency, and improving ACLR by as much as 8dB. The polar transmitter is characterized over a supply voltage of 2.5-4.5V, making it well suited for battery powered, handheld applications.     

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.     

A 2 W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters

This paper presents a hybrid switching amplitude modulator for class-E2 EDGE polar transmitters. To achieve both high efficiency and high speed, it consists of a wideband buffered linear amplifier as a voltage source and a PWM switching amplifier with a 2 MHz switching frequency as a dependent current source. The linear amplifier with a novel class-AB topology has a high current-driving capability of approximately 300 mA with a bandwidth wider than 10 MHz. It can also operate on four quadrants with very low output impedance of about 200 at the switching frequency attenuating the output ripple voltage to less than 12 . A feedforward path, a PWM control, and a third-order ripple filter are used to reduce the current burden of the linear amplifier. The output voltage of the hybrid modulator ranges from 0.4 to 3 V for a 3.5 V supply. It can drive an RF power amplifier with an equivalent impedance of 4 up to a maximum output power of 2.25 W with a maximum efficiency of 88.3%. The chip has been fabricated in a 0.35 m CMOS process and occupies an area of 4.7 .     

一种双耦合双混频中频信号功率反馈电路

在自动电平控制系统中,常用功率反馈电路存在一个主要限制:调幅动态范围受限于电平检波器和相关电路,使其远远低于线性调制器的功率可变范围。文中介绍了一种双耦合双混频中频信号功率反馈电路,使检波器只需检测固定中频信号的功率大小即可反馈调节射频输出信号的功率幅度。经测试,电路射频输入信号在24 GHz变化时,得到的中频信号频率固定不变,等于晶振信号54 MHz。线性调制器的衰减量在031.5 dB变化时,中频信号功率与射频输出信号功率成良好的线性关系,满足预期的设计要求。     

应用于无线传感器网络的功率放大器的设计

给出一种基于TSMC 0.18 μm RF CMOS工艺,应用于无线传感器网络的2.4 GHz 功率放大器的设计.该功率放大 器工作频率范围为2.4 GHz～2.4835 GHz,采用全差分AB类共源共栅电路结构,使用功率控制技术以节省功耗,当输入信号 功率-12.5 dBm时,输出功率在-10.4 dBm至5.69 ...     

Adaptive digital/RF predistortion using a nonuniform LUT indexing function with built-in dependence on the amplifier nonlinearity

This paper reports on an integrated adaptive digital/RF predistorter using a nonuniform spaced lookup table (LUT) and in-phase/quadrature (I/Q) RF vector multiplier (VM). The LUT contents are directly deduced from the baseband input and output signals of the power amplifier (PA). In addition, a new nonlinear indexing function of the predistortion LUT with built-in dependence on the PA nonlinearity is proposed. This function is made to be robust to the input signal statistics. A comparison of this new indexation method with conventional approaches, namely, power and logarithmic power indexation functions, is carried out. The superiority of the proposed scheme is demonstrated in particular for class-AB amplifiers where the gain of the PA varies over the whole input range of the drive signal. The measured output spectrum of a linearized 90-W peak lateral double-diffused metal-oxide-semiconductor PA reveals a significant reduction of the power emission at the adjacent channels of approximately 15 dB under IS95, single-carrier, and multicarrier wide-band code-division multiple-access signals. The experimental evaluation is carried out using an RF/digital predistorter prototype that mainly includes an envelope detector, a linear I/Q RF VM, field-programmable gate array and digital signal processor, and fast analog/digital and digital/analog converters.     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

A hybrid digital/RF envelope predistortion linearization system for power amplifiers

This paper presents an adaptive wide-band digitally controlled RF envelope predistortion linearization system for power amplifiers (PAs). A field-programmable gate-array-based lookup table is indexed by a digitized envelope power signal, and instantaneously adjusts the input signal amplitude and phase via an RF vector modulator to compensate for the AM-AM and AM-PM distortion. The advantages of this predistortion architecture over conventional baseband digital approaches are that a 20%-33% wider correction bandwidth is achievable at the same clock speeds, and linearization can be performed without the need for a digital baseband input signal. The timing match between the input RF signal and predistorting signal, which is one of the critical factors for performance, was investigated and adjusted to obtain optimum performance. Using three-carrier cdmaOne and wide-band multitone signals, the linearization performances for a 0.5-W GaAs heterostructure field-effect transistor, a 90-W peak-envelope-power (PEP) silicon LDMOS PA, and a 680-W PEP LDMOS PA were examined. In addition, the predistortion performance variation for different signals was studied in terms of signal envelope statistics, output powers, and PA power capacities.     

A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers

In this paper, a novel digital predistortion assisted supply modulator is presented. The proposed modulator is suitable for envelope tracking power amplifiers. In this topology, a digitally controlled linear power amplifier is used to compensate the switching noise ripples of the switching modulator. The proposed structure is evaluated with a 0.18 µm CMOS process technology. The results show up to 9% static efficiency improvement in comparison with previous one-phase and two-phase architectures. It is shown that for a 5 MHz WiMAX signal with a 6.7 dB PAPR at 26.8 dBm output power, a maximum average efficiency of 73.5% is achieved in the proposed design.     

A CMOS RF Polar Transmitter of a UHF Mobile RFID Reader for High Power Efficiency

A CMOS radio frequency (RF) polar transmitter architecture for a UHF (860–960 MHz) RF identification (RFID) reader is proposed, which consists of a switch-mode CMOS power amplifier (PA) and an analog pulse-shaping filter implemented in 0.25-$mu$ m CMOS process. The amplitude modulation of a amplitude shift keying signal is performed by simply switching the common gate transistor of a cascode power amplifier. Extremely low power consumption is achieved when the PA is switched off. The power efficiency of the transmitter is enhanced not only by using switching power amplifier but also by employing this architecture.      

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.