Reduced clock swing domino logic

A reduced clock swing domino logic gate for 50% reduction in power consumption in clock networks is presented. The original full swing gate works properly at reduced swing with a better noise tolerance and small loss of performance while simple resizing allows the same speed, power and noise figures     

Latched domino CMOS logic

A new gate configuration, the latched domino (Ldomino) CMOS gate, is presented. It can be used to alleviate the inversion problem inherent in domino CMOS, while improving speed and reducing layout area. Ldomino logic can serve as an efficient interface stage between blocks of static and domino or differential-cascode voltage-switch logic. The function of interfacing single-ended logic signals to differential domino-compatible logic signals is combined with the capability of efficient implementation of complex logic functions, thereby improving the logic flexibility of domino logic. A simple 4-bit ALU is used as an illustrative example of the application of Ldomino logic.     

Latched domino CMOS logic

A new gate configuration: the latched domino (Idomino) CMOS gate is described in the letter. It can be used to alleviate the inversion problem inherent in domino CMOS logic. It retains the speed advantages of domino logic while improving logic flexibility and reducing area. The gate is compatible with standard domino logic.     

A new, precharged, low-power logic family for GaAs circuits

We present a new precharged, low-power logic family in GaAs that operates at speeds comparable to DCFL and consumes about one-fourth the power of DCFL. It uses a 2 V power supply for operation and can be used in conjunction with the widely used DCFL circuits. The logic family allows us to build complex gates in one gate delay, provides better noise margins, and is less susceptible to load capacitances than an unbuffered DCFL gate, thus making it useful for standard-cell based designs. To verify the approach, we have designed and fabricated a fully functional test chip containing a precharged full adder     

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.     

A low-leakage and NBTI-mitigated N-type domino logic

NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDo, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.     

Testability enhancement of domino CMOS logic

A simple circuit technique to enhance the testability of domino CMOS circuits is presented. The fact that domino CMOS gates always have their outputs precharged low enables one to test for output stuck-at-one faults by a simple modification of the domino gate.     

GaAs capacitively coupled domino logic gate

A novel GaAs capacitively coupled domino logic (CCDL) gate is proposed. Derived from capacitor-coupled logic, this domino gate offers complex gate design capability with relatively low power dissipation and high speed, making it suitable for VLSI implementations.<>     

A technique for Improving dual-output domino logic

We present a technique, termed clock-generating (CG) domino, for improving dual-output domino logic that reduces area, clock load and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24%, respectively, over dual-output domino and a 48% power reduction for the largest circuit.     

FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.     

Fast adders using enhanced multiple-output domino logic

Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in. Based on this result, a new sparse carry chain architecture is proposed for the CLA adder. We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a consequent reduction in the number of stage delays. Using a 1.2-μm CMOS technology, we verify our simulation procedures by fabrication and measurement of a 2.7 ns critical path     

Improved domino logic for high speed design

Techniques are introduced to improve the speed of domino logic. With an inverted clock scheme, a serial transistor is removed and capacitances at the output node are reduced in the new structures. HSPICE simulation shows that over 20% performance enhancement is achieved.     

Noise-aware interconnect power optimization in domino logic synthesis

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized, which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption about 14% on average.     

High-speed domino logic based on transition-forwarding andsteepest-descent method

Single-end domino logic is widely used in high-performance processor designs. A new structure for high-speed single-end domino logic is presented which minimises both the precharge and the evaluation times. The new structure based on transition-forwarding and the steepest descent technique achieves a ~47% increase in speed over improved domino logic     

Coupling-aware minimum delay optimisation for domino logic circuits

Minimum delay associated with the hold time requirement is a concern to circuit designers, since race-through hazards are inherent to any multiple clock organisation or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates that minimum-delay path failure through coupling induced speedup. To tackle the minimum-delay problem for domino logic, we propose a minimum-delay optimisation algorithm considering coupling effects. Experimental results indicate that our algorithm fields a significant increase of minimum-delay without incurring maximum-delay violation     

Mixed static and domino logic on the CMOS gate forest

In a semicustom design environment with unified transistor geometries, logic circuit optimization is achieved using an efficient physical circuit implementation. In particular, the semicustom realization of domino logic is demonstrated with a standard-cell and a multiplier design which are used to support the implementation of such a dynamic logic design style on a gate forest, which has a higher n count than p count. The mixture of complementary and dynamic logic allows the designer to improve the critical-path delay and to reduce the size of the layout. The domino standard-cell architecture supports multiple-output configurations and additional internal precharge. The operation time for a mixed static/dynamic multiplier is approximately 30% higher than that of the static version based on a carry select adder. This difference mainly affects the critical delay of the sign-extension path of the parallel adder array     

Dynamic GaAs capacitively coupled domino logic (CCDL)

Dynamic capacitively coupled domino logic (CCDL) has been proposed as a practical means of implementing low-power and high-speed complex gates. The CCDL gate delay characteristics obtained from an analytical model and from test circuits implemented in a 1-μm GaAs E/D process are presented. In addition, the feasibility of using CCDL gates to implement practical circuits is demonstrated by the experimental characterization of a 4-b carry-lookahead adder. The adder has a critical delay of 1.1 ns and a power dissipation of 96 mW. A comparison of the dynamic CCDL adder with conventional static designs indicates the advantages of dynamic CCDL gates in reducing power dissipation and increasing speed, making such gates suitable for VLSI implementations     

Robustness aware high performance high fan-in domino OR logic design

A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper. Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also, a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.     

Testing of multiple-output domino logic (MODL) CMOS circuits

Techniques for testing MODL circuits are presented. It is shown that, due to the greater observability of MODL circuits, their test sets can be considerably small than those derived for the conventional domino CMOS circuits. Tests for faults are derived from a comprehensive fault model which includes stuck-at, stuck-open, and stuck-on faults. Test sets for MODL circuits are inherently robust in the presence of circuit delays and timing skews at the inputs. They are also well-protected against the charge distribution problem. It is thus concluded that MODL is an attractive CMOS logic technique     

抗噪声和工艺参数浮动的高性能多输入多米诺或门设计

A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper.Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also,a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.