AlGaN/GaN self-aligned MODFET with metal oxide gate for millimeter wave application

As promising candidates for future microwave power devices, GaN-based high-electron mobility transistors (HEMTs) have attracted much research interest. An investigation of the operation of AlGaN/GaN n type self-aligned MOSFET with modulation doped GaN channels is presented. Liquid phase deposited (LPD) SiO₂ is used as the insulating material. An analytical model based on modified charge control equations is developed. The investigated critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak DC trans-conductance (g_m), break down voltage (V_br) and unity current gain cut-off frequency (f_T). The typical DC characteristics for a gate length of 1 μm with 100 μm gate width are following: I_max=800 mA/mm, V_break-down=50 V, g_{m_extrinsic}=200 mS/mm, V_pinchoff=−10 V. The analysis and simulation results on the transport characteristics of the MOS gate MODFET structure is compared with the previously measured experimental data. The calculated values of f_T (20-130 GHz) suggest that the operation of the proposed device effectively, has sufficiently high current gain cutoff frequencies over a wide range of drain voltage, which is essential for high-power performance at microwave frequencies. The proposed device offers lower on-state resistance. The results so obtained are in close agreement with the experimental data.     

Annealing effect on the metal gate effective work function modulation for the Al/TiN/SiO2/p-Si structure

In this work, the thermal annealing effect on the metal gate effective work function (EWF) modulation for the Al/TiN/SiO₂/p-Si(1 0 0) structure was investigated. Compared with the sample of TiN/SiO₂/p-Si(1 0 0) structure, for the sample additionally capped with Al the flat band voltage has a very obvious shift as large as 0.54 V to the negative direction after forming gas annealing. It is also revealed that the thermal budget can effectively influence both the EWF of the gate electrode and the thickness of the gate dielectric layer when a post annealing at 600 °C with different soak times was applied to the samples with Al cap. Material characterization indicates that the diffusion of Al and the formation of Al oxide during annealing should be responsible for all the phenomena. The interface trap density Dit calculated from the high-frequency C-V and the laser-assisted high-frequency C-V curves show that the introduction of Al does not cause reliability problem in the Al/TiN/SiO₂/p-Si structure.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

The effect of pulsed laser annealing on the nickel silicide formation

The pulsed laser annealing (PLA) is used to assist nickel silicide transformation for Schottky barrier height reduction and tensile strain enhancement and the effect of different laser power are investigated. In this report, a two-step annealing process which combine the conventional rapid thermal annealing with pulsed laser annealing is proposed to achieve a smooth silicon-rich NiSi_x interfacial layer on (1 0 0) silicon. With optimized laser energy, a 0.2 eV Schottky barrier height (SBH) modulation is observed from Schottky diode electrical characterization. Furthermore, PLA provides sufficient effective temperature during silicidation which also lead to increased tensile stress of silicide film than the two-step RTA silicide is also investigated. The SBH modulation and tensile stress enhancement benefits of PLA silicidation are considered as an alternative to the conventional rapid thermal annealing for ultra-scaled devices performance enhancement.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

Effect of axial halogen substitution on the performance of subphthalocyanine based organic photovoltaic cells

To probe the influence of molecular dipole on the open circuit voltage (V_OC) of molecular heterojunction organic solar cells, we study axially fluorinated boron subphthalocyanine/fullerene (SubPc-F/C₆₀) junctions. These exhibit an open-circuit voltage V_OC = 1.00 V, a value closer to the HOMO–LUMO offset at the donor–acceptor interface = 1.69 eV than the V_OC = 1.06 V measured for junctions between the archetypal chlorinated SubPc and C₆₀, with corresponding HOMO–LUMO offset = 1.84 eV. Aside from the axial halogen substitution, the two compounds exhibit similar molecular structure and optical absorption. The energy levels and structure of the heteromolecular polaron pair are calculated, and the ideal organic diode model for SubPc-Cl is modified accordingly, successfully reproducing the experimental SubPc-F device characteristics. The reproducible difference in V_OC is attributed to the different electric dipole strength between SubPc-F and SubPc-Cl and its influence on polaron pair dynamics at the heterojunction.     

A flip-chip packaged 80-nm In0.7Ga0.3As MHEMT for millimeter-wave low-noise applications

In this paper, we present a flip-chip 80-nm In_0.7Ga_0.3As MHEMT device on an alumina (Al₂O₃) substrate with very little decay on device RF performance up to 60 GHz. After package, the device exhibited high I_DS = 435 mA/mm at V_DS = 1.5 V, high g_m = 930 mS/mm at V_DS = 1.3 V, the measured gain was 7.5 dB and the minimum noise figure (NF_min) was 2.5 dB at 60 GHz. As compared to the bare chip, the packaged device exhibited very small degradation in performance. The result shows that with proper design of the matching circuits and packaging materials, the flip-chip technology can be used for discrete low noise FET package up to millimeter-wave range.     

New ISFET interface circuit design with temperature compensation

An integrated and new interface circuit with temperature compensation has been developed to enhance the ISFET readout circuit stability. The bridge-type floating source circuit suitable for sensor array processing has been proposed to maintain reliable constant drain-source voltage and constant drain current (CVCC) conditions for measuring the threshold voltage variation of ISFET due to the corresponding hydrogen ion concentration in the buffer solution. The proposed circuitry applied to Si₃N₄ and Al₂O₃-gate ISFETs demonstrate a variation of the drain current less than 0.1 μA and drain-source voltage less than 1 mV for the buffer solutions with the pH value changed from 2 to 12. In addition, the scaling circuitry with the V_T temperature correction unit (extractor) and LABVIEW software are used to compensate the ISFET thermal characteristics. Experimental results show that the temperature dependence of the Si₃N₄-gate ISFET sensor improved from 8 mV/°C to less than 0.8 mV/°C.     

Effects of active area and gate doping method on program threshold voltage in an EEPROM cell

In this paper, we investigate dependency of program threshold voltage (V_T) in EEPROM cell on active area and doping method of floating gate. With in situ doped floating gate, it is found that there is a sharp drop of program V_T from 4 to 2.25 V when the channel width is reduced from 0.30 to 0.22 μm, while doping by ion implantation results in slight reduction of program V_T from 3.95 to 3.69 V. It also appears that channel length is another critical factor to affect on reduction of program V_T. In case of in situ doped floating gate, the program V_T is reduced from 3.9 to 2.7 V when the channel length is reduced from 0.20 to 0.18 μm. TEM analysis reveals that thermal oxidation in tunnel oxide region occurs during subsequent high temperature oxidation due to oxidant penetration via interface of silicon surface and sidewall silicon nitride.     

Resistive switching characteristics of ultra-thin TiOx

We investigated the resistive switching characteristics of Ir/TiO_x/TiN structure with 50 nm active area. We successfully formed ultra-thin (4 nm) TiO_x active layer using oxidation process of TiN BE, which was confirmed by X-ray Photoelectron Spectroscopy (XPS) depth profiling. Compared to large area device (50 μm), which shows only ohmic behavior, 250 and 50 nm devices show very stable resistive switching characteristics. Due to the formation and rupture of oxygen vacancies induced conductive filament at Ir and TiO_x interface, bipolar resistive switching was occurred. We obtained excellent switching endurance up to 10⁶ times with 100 ns pulse and negligible degradation of each resistance state at 85 °C up to 10⁴ s.     

Effect of H2O evolving from TEOS based SiO2 film on the EEPROM cell characteristic

In this paper, we investigate the effect of water (H₂O) molecules evolving from silicon dioxide (SiO₂) film deposited by low pressure chemical vapor deposition (LPCVD) at 670 °C on the transistor characteristic of an electrically erasable programmable read only memory (EEPROM) cell. Fourier Transform Infra red (FT-IR) analysis reveals that H₂O is captured during film deposition and diffused to silicon surface during high thermal processing. The diffused H₂O molecules lower threshold voltage (V_t) of cell transistor and, thus, leakage current of the cell transistor is increased. In erased cell, V_t lowering is 0.25 V in which it increases leakage current of cell transistor from 1 to 100 pA. This results in the lowering of high voltage margin of a 512 Kb EEPROM from 2.8 to 2.6 V at 85 °C.     

Low cost bulk-silicon CDMOS technology and enhanced dv/dt high voltage driver circuit for PDP data driver IC

In this paper, a 256-channel data driver IC for plasma display panels (PDPs) is proposed. A new low cost 0.5 μm bulk-silicon CDMOS (CMOS and DMOS) technology is developed, resulting in the improvement of input data frequency up to 120 MHz and reduction of die cost about 20% compared with the conventional one. A novel high voltage driver circuit is also presented to optimize dv/dt of the output signal from 1.2 to 0.2 V/ns. The proposed circuit can avoid unwanted turning on of the pLEDMOS transistors in output stage and cut down the power dissipation by 12% compared with the conventional one. The application results show rising and falling times of the output stage are 45 and 84 ns, respectively.     

The profile of temperature and voltage dependent series resistance and the interface states in (Ni/Au)/Al0.3Ga0.7N/AlN/GaN heterostructures

The temperature dependence of capacitance-voltage (C-V) and the conductance-voltage (G/w-V) characteristics of (Ni/Au)/Al_0.3Ga_0.7N/AlN/GaN heterostructures were investigated by considering the effect of series resistance (R_s) and interface states N_ss in a wide temperature range (79-395 K). Our experimental results show that both R_s and N_ss were found to be strongly functional with temperature and bias voltage. Therefore, they affect the (C-V) and (G/w-V) characteristics. The values of capacitance give two peaks at high temperatures, and a crossing at a certain bias voltage point (∼3.5 V). The first capacitance peaks are located in the forward bias region (∼0.1 V) at a low temperature. However, from 295 K the second capacitance peaks appear and then shift towards the reverse bias region that is located at ∼−4.5 V with increasing temperature. Such behavior, as demonstrated by these anomalous peaks, can be attributed to the thermal restructuring and reordering of the interface states. The capacitance (C_m) and conductance (G/w-V) values that were measured under both reverse and forward bias were corrected for the effect of series resistance in order to obtain the real diode capacitance and conductance. The density of N_ss, depending on the temperature, was determined from the (C-V) and (G/w-V) data using the Hill-Coleman Method.     

Electrical properties of vacuum annealed La2O3 thin films grown by E-beam evaporation

In this article, the conduction mechanisms of metal-oxide-semiconductor with vacuum annealed Lanthana (La₂O₃) oxide film are investigated. Lanthana films with thicknesses of 3.5, 4.7, and 11 nm were deposited by E-beam evaporation on n-Si (100), and annealed at various temperatures (300-500 °C) in ultra-high vacuum (10⁻¹⁰-10⁻⁹ Torr) for 90 min. From the measurement of spectroscopic ellipsometry, it is found that film thickness is increased with annealing temperature, which would be cause of flat-band voltage shift (ΔV_FB) due to the growth of interfacial layer. From the capacitance measurement, it is found that ΔV_FB of the film is reduced by post-deposition anneal (PDA) compared to that of as-deposited film, but increase again at high temperature annealing, especially in the case of thin film (3.5 nm). From the applied voltage and temperature dependence of the leakage current of the film, with different gate electrode materials (Ag, Al, and Pt), it is shown that the leakage currents are associated with ohmic and Poole-Frenkel (P-F) conductions when flat-band voltage (V_FB) is less than zero, and ohmic and Space-Charge-Limited Current (SCLC) conductions when V_FB is greater than zero. The dielectric constants obtained from P-F conduction for Al gate electrode case is found to be 11.6, which is consistent with the C-V result 11.9. Barrier height of trap potential well is found to be 0.24 eV from P-F conduction. Based on SCLC theory, leakage currents of 3.5 and 11 nm films with different PDA temperatures are explained in terms of oxide trap density.     

Epitaxial growth of Dy2O3 thin films on epitaxial Dy-germanide films on Ge(0 0 1) substrates

Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGe_x films. Thin films of Dy₂O₃ are grown on the DyGe_x film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGe_x films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGe_x films with (0 0 1) orientations. After the growth of Dy₂O₃ films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy₂O₃ films is smooth with a root mean square roughness of 10 Å.     

High performance TaYOx-based MIM capacitors

TaYO_x-based metal-insulator-metal (MIM) capacitors with excellent electrical properties have been fabricated. Ultra-thin TaYO_x films in the thickness range of 15-30 nm (EOT ∼ 2.4-4.7 nm) were deposited on Au/SiO₂ (100 nm)/Si (100) structures by rf-magnetron co-sputtering of Ta₂O₅ and Y₂O₃ targets. TaYO_x layers were characterized by X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray (EDX) and X-ray diffraction (XRD) to examine the composition and crystallinity. An atomic percentage of Ta:Y = 58.32:41.67 was confirmed from the EDX analysis while XRD revealed an amorphous phase (up to 500 °C) during rapid thermal annealing. Besides, a high capacitance density of ∼3.7-5.4 fF/μm² at 10 kHz (ε_r ∼ 21), a low value of VCC (voltage coefficients of capacitance, α and β) have been achieved. Also, a highly stable temperature coefficient of capacitance, TCC has been obtained. Capacitance degradation phenomena in TaYO_x-based MIM capacitors under constant current stressing (CCS at 20 nA) have been studied. It is observed that degradation depends strongly on the dielectric thickness and a dielectric breakdown voltage of 3-5 MV/cm was found for TaYO_x films. The maximum energy storage density was estimated to be ∼5.69 J/cm³. Post deposition annealing (PDA) in O₂ ambient at 400 °C has been performed and further improvement in device reliability and electrical performances has been achieved.     

ALD of LaHfOx nano-laminates for high-κ gate dielectric applications

Electrical properties and thermal stability of LaHfO_x nano-laminate films deposited on Si substrates by atomic layer deposition (ALD) have been investigated for future high-κ gate dielectric applications. A novel La precursor, tris(N,N′-diisopropylformamidinato) lanthanum [La(ⁱPrfAMD)₃], was employed in conjunction with conventional tetrakis-(ethylmethyl)amido Hf (TEMA Hf) and water (H₂O). The capacitance-voltage curves of the metal oxide semiconductor capacitors (MOSCAPs) showed negligible hysteresis and frequency dispersion, indicating minimal deterioration of the interface and bulk properties. A systematic shift in the flat-band voltage (V_fb) was observed with respect to the change in structure of nano-laminate stacks as well as La₂O₃ to HfO₂ content in the films. The EOTs obtained were in the range of ∼1.23-1.5 nm with leakage current densities of ∼1.3 × 10⁻⁸ A/cm² to 1.3 × 10⁻⁵ A/cm² at V_fb − 1 V. In addition, the films with a higher content of La₂O₃ remained amorphous up to 950 °C indicating very good thermal stability, whereas the HfO₂ rich films crystallized at lower temperatures.     

Interfacial microstructure and electrical properties of HfAlOx thin films on compressively strained Si83Ge17 grown by RF magnetron sputtering

Interfacial microstructure and electrical properties of HfAlO_x films deposited by RF magnetron sputtering on compressively strained Si₈₃Ge₁₇/Si substrates were investigated. HfSiO_x-dominated amorphous interfacial layer (IL) embedded with crystalline HfSi_x nano-particles were revealed by high resolution transmission electron microscopy (HRTEM) and X-ray photoelectron spectroscopy depth profile study. About 280 mV-wide clockwise capacitance-voltage(C-V) hysteresis for the HfAlO_x film deposited in Ar + N₂ mixed ambient was observed. Oxygen vacancies and interfacial defects in the HfSiO_x IL, as well as trapped charges in the boundaries between the HfSi_x nano-particles and surrounded amorphous HfSiO_x may be responsible for the large C-V hysteresis.     

Temperature dependent current-voltage characteristics of n-MgxZn1−xO/p-GaN junction diodes

This study investigates the temperature dependence of the current-voltage (I-V) characteristics of n-Mg_xZn_1−xO/p-GaN junction diodes. The n-Mg_xZn_1−xO films were deposited on p-GaN using a radio-frequency (rf) magnetron sputtering system followed by annealing at 500, 600, 700, and 800 °C in nitrogen ambient for 60 s, respectively. The n-Mg_xZn_1−xO/p-GaN diode at a substrate temperature of 25 °C had the lowest leakage current in reverse bias. However, the leakage current of the diodes increased with an increase in annealing temperatures. The temperature sensitivity coefficients of the I-V characterizations were obtained at different substrate temperatures (25, 50, 75 100, and 125 °C) providing extracted values of 26.4, 27.2, 17.9, and 0.0 mV/°C in forward bias and 168.8, 143.4, 84.6, and 6.4 mV/°C in reverse bias, respectively. The n-Mg_xZn_1−xO/p-GaN junction diode fabricated with Mg_xZn_1−xO annealed at 800 °C demonstrated the lowest temperature dependence. Based on these findings, the n-Mg_xZn_1−xO/p-GaN junction diode is feasible for GaN-based heterojunction bipolar transistors (HBTs).     

Circuital modelling of S-shape removal in the current–voltage characteristic of TiOx inverted organic solar cells through white-light soaking

In this work light activation phenomenon in inverted bulk heterojunction (BHJ) organic solar cells (OSC) has been electrically modelled with a two-diode equivalent circuit. OSC are based on poly(3-hexylthiophene) (P3HT): 1-(3-methoxycarbonyl)-propyl-1-1-phenyl-(6,6) C61 (PCBM) with a titanium oxide (TiO_x) sublayer. Current–voltage (I–V) characteristics show a highly pronounced S-shape that is gradually removed during light activation process. The circuit used to model I–V curves includes two diodes in forward and reverse bias together with two parallel resistances, R_P1 and R_P2. The parallel of the reverse bias diode and its corresponding resistance R_P2 models the electrical behaviour of the TiO_x interlayer. This interlayer has been thermally treated at different temperatures, from 80 °C up to 180 °C, reducing the activation time from 400 s for unbaked devices down to 30 s for devices annealed at temperatures higher than 80 °C. The S-shape shown in the I–V characteristic is completely removed after a few minutes of white-light illumination. I–V curves recorded during the activation process have been fitted with the analytical solution of the two-diode circuit based on W-Lambert function. A decrease of the subcircuit 2 equivalent resistance has been found to be the cause of S-shape removal. This resistance diminishing is in good agreement with the increase of TiO_x conductance with baking temperature and white-light exposure time found by other authors.