Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

High-efficiency test pattern generating mechanism

A high-efficiency test pattern generating mechanism blending the weighted-random-pattern generator and the controllable-linear-feedback-shift register is proposed in this paper. This mechanism tests a logic circuit in two phases. In the first phase, the weighted-random-pattern generator generates the test patterns to drop some of the faults from the fault list containing the faults that have not been tested in the initial testing performed by the patterns generated from the automatic-test-pattern generator. In the second phase, the controllable-linear-feedback-shift register generates the test patterns to test the deterministic faults that have not been tested in the first phase. We adopt controllable-linear- feedback-shift register to generate the deterministic patterns instead of modifying the configuration of the weighted-random-pattern generator such that a better fault coverage can be achieved with a lower hardware penalty and a shorter test length.     

基于可配置LFSR的低功耗确定性矢量生成技术的研究

针对组合电路内建自测试过程中的功耗和故障覆盖率等问题,提出了一种能获得较高故障覆盖率的低功耗测试矢量生成方案。该方案先借助A talanta测试矢量生成工具,针对不同的被测电路生成故障覆盖率较高的测试矢量,再利用插入单跳变测试矢量的方法以及可配置线性反馈移位寄存器生成确定性测试向量的原理,获得低功耗测试矢量。通过对组合电路集ISCAS’85的实验,证实了这种测试生成方案的有效性。     

A Ring Architecture Strategy for BIST Test Pattern Generation

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].     

在基于LFSR重播种的压缩环境下同时降低测试数据量和测试功耗

集成电路测试中过高的测试功耗和日益增长的测试数据量是半导体工业面临的两大问题。本文提出了一种在基于线性反馈移位寄存器重播种的压缩环境下基于扫描块的测试向量编码方案。同时,本文也介绍了一种新颖的扫描块重聚类算法。本文的主要贡献是给出了一种灵活的测试应用框架,它能够极大地减少扫描移位期间的跳变个数和经由LFSR重播种生成的确定位的数目。因此,文中方案能够极大地降低测试功耗和测试数据量。在ISCAS’89基准电路上使用Mintest测试集进行的实验表明,本文方法能够减少72%-94%的跳变,并且能获得高达74%-94%的测试压缩率。     

基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高。针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法。该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列。在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度。分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率。     

基于双模式LFSR的低功耗BIST结构

传统的BIST结构中,由于LFSR产生大量的测试矢量在测试过程中消耗了大量的功耗。为了减少测试矢量的数目而不影响故障覆盖率,我们提出了一种新的基于双模式LFSR的低功耗BIST结构。首先介绍了功耗模型和延迟模型的基础知识,然后给出了用于生成双模式LFSR的矩阵,并介绍了解矩阵方程式的算法。随后说明了新的BIST结构和用于矢量分组的模拟退火算法。最后,基于Benchmark电路的实验证明这种结构可以在不降低故障覆盖率的同时减少70％的功耗。     

基于线性反馈移位寄存器和CSA算法的CA系统加扰模块设计

简要介绍CA系统及其加扰模块，具体分析选用线性反馈移位寄存器作伪随机序列发生器、采用CSA算法作为加扰算法的一种CA系统加扰模块的设计方案，前者易于硬件实现、后者易于软件实现使得该方案具有可行性。     

基于线性反馈移位寄存器和CSA算法的CA系统加扰模块设计

简要介绍CA系统及其加扰模块,具体分析选用线性反馈移位寄存器作伪随机序列发生器、采用CSA算法作为加扰算法的一种CA系统加扰模块的设计方案,前者易于硬件实现、后者易于软件实现使得该方案具有可行性。     

An efficient architecture for accumulator-based test generation of SIC pairs

Research conducted over the years has shown that the application of single input change (SIC) pairs of test patterns for sequential, i.e. stuck-open and delay fault testing is extremely efficient. In this paper, a novel architecture for the generation of SIC pairs is presented. The implementation of the proposed architecture is based on Ling adders that are commonly utilized in current data paths due to their high-operating speed. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.     

Reducing test-data volume and test-power simultaneously in LFSR reseeding-based compression environment

This paper presents a new test scheme based on scan block encoding in a linear feedback shift register (LFSR) reseeding-based compression environment.Meanwhile,our paper also introduces a novel algorithm of scan-block clustering.The main contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during scan shift and the number of specified bits that need to be generated via LFSR reseeding.Thus,it can significantly reduce the test power and test data volume.Experimental results using Mintest test set on the larger ISCAS’89 benchmarks show that the proposed method reduces the switching activity significantly by 72%-94%and provides a best possible test compression of 74%-94%with little hardware overhead.     

Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults

This paper presents a combinatorial method of evaluating the effectiveness of linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSR) as generators for stimulating faults requiring a pair of vectors. We provide a theoretical analysis and empirical comparisons to see why the LHCA are better than the LFSRs as generators for sequential-type faults in a built-in self-test environment. Based on the concept of a partner set, the method derives the number of distinctk-cell substate vectors which have 2^2k , 1k[n/2], transition capability for ann-cell LHCA and ann-cell LFSR with maximum length cycles. Simulation studies of the ISCAS85 benchmark circuits provide evidence of the effectiveness of the theoretrical metric.This work was supported in part by Reserach Grants No. 5711 and No. 39409 and a Strategic Grant from the Natural Sciences and Engineering Research Council of Canada and by an equipments loan from the Canadian Microelectronics Corporation.A preliminary version of this paper is partially presented at theIEEE ISCAS'94, May 1994.     

Pseudorandom BIST for test and characterization of linear and nonlinear MEMS

In this paper we study the use of the pseudorandom (PR) technique for test and characterization of linear and nonlinear devices, in particular for micro electro mechanical systems (MEMS). The PR test technique leads to a digital built-in-self-test (BIST) technique that is accurate in the presence of parametric variations, noise tolerant, and has high-quality test metrics. We will describe the use of the PR test technique for testing linear and nonlinear MEMS, where impulse response samples of the device under test are considered to verify its functionality. Next, we illustrate and evaluate the application of this technique for linear and nonlinear MEMS characterization.     

内建自测试的测试生成方法研究

内建自测试（BIST）方法是目前可测试性设计（DFT）中应用前景最好的一种方法,其中测试生成是关系BIST性能好坏的一个重要方面。测试生成的目的在于生成尽可能少的测试向量并用以获得足够高的故障覆盖率,同时使得用于测试的硬件电路面积开销尽可能低、测试时间尽可能短。内建自测试的测试生成方法有多种,文中即对这些方法进行了简单介绍和对比研究,分析了各自的优缺点,并在此基础上探讨了BIST面临的主要问题及发展方向。     

Self-test of sequential circuits with deterministic test pattern sequences

This article describes a new approach for synthesizing a cost-efficient self-test hardware for a given set of deterministic test pattern sequences. To minimize the test hardware effort instead of all the test sequences, only a very small subset will be selected such that a simple generation of all necessary test sequences will be ensured. This procedure drastically decreases the storage requirements (about 80%) and therefore distinctly reduces the necessary test hardware overhead. Experimental results on the ISCAS-S-benchmarks emphasize the efficiency of our approach.This work is supported by the ESPRIT project 6855 (LINK).     

On Using Twisted-Ring Counters for Test Set Embedding in BIST

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits.Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.     

Design for Delay Testability in High-Speed Digital ICs

The cost-effective testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, costly testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a Design for Delay Testability (DfDT) technique such that high-speed ICs can be tested using inexpensive, low-speed test systems. Also extensions for possible full BIST of delay faults are addressed.     

An Efficient Built‐in Self‐Test Algorithm for Neighborhood Pattern‐ and Bit‐Line‐Sensitive Faults in High‐Density Memories

As the density of memories increases, unwanted interference between cells and the coupling noise between bit‐lines become significant, requiring parallel testing. Testing high‐density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built‐in self‐test (BIST) algorithm for neighborhood pattern‐sensitive faults (NPSFs) and new neighborhood bit‐line sensitive faults (NBLSFs). Instead of the conventional five‐cell and nine‐cell physical neighborhood layouts to test memory cells, a four‐cell layout is utilized. This four‐cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck‐at faults, transition faults, conventional pattern‐sensitive faults, and neighborhood bit‐line sensitive faults.     

Scan power-aware deterministic test scheme using a low-transition linear decompressor

Growing test data volume and excessive testing power are both serious challenges in the testing of very large-scale integrated circuits. This article presents a scan power-aware deterministic test method based on a new linear decompressor which is composed of a traditional linear decompressor, k-input AND gates and T flip-flops. This decompression architecture can generate the low-transition deterministic test set for a circuit under test. When applying the test patterns generated by the linear decompressor, only a few transitions occur in the scan chains, and hence the switching activity during testing decreases significantly. Entire test flow compatible with the design is also presented. Experimental results on several large International Symposium on Circuits and Systems’89 and International Test Conference’99 benchmark circuits demonstrate that the proposed methodology can reduce test power significantly while providing a high compression ratio with limited hardware overhead.     

A class of two-dimensional cellular automata and their applications in random pattern testing

A basic framework to characterize the behavior of two-dimensional (2-D) cellular automata (CA) has been proposed. The performance of the regular structure of the 2-D CA has been evaluated for pseudo-random pattern generation. The potential increase in the local neighborhood structure for 2-D CA has led to better randomness of the generated patterns as compared to LFSR and 1-D CA. The quality of the random patterns generated with 2-D CA based built-in-self-test (BIST) structure has been evaluated by comparing the fault coverage on several benchmark circuits. Also a method of synthesizing 2-D CAs to generate patterns of specified length has been reported. The patterns generated can serve as a very good source of random two-dimensional sequences and also variable length parallel pattern generation having virtually nil correlation among the bit patterns.