片内光通信技术综述

在纳米工艺水平下,传统的铜线互连已经很难满足集成电路芯片在延迟、带宽、功耗等方面的要求,片内通信问题已经成为集成电路设计的瓶径.文中根据片内光器件集成技术的最新进展,介绍了采用片内光互连代替电互连的最新技术及其性能方面的优势.文中重点总结了片内光互连的三种典型应用.首先,介绍了片内光时钟分布网络;其次,从应用的角度分析了光电总线结构相对于单纯电总线在性能上的提升;最后,介绍了一种新的片上光网络,它集成了片内电的包交换控制网络和宽带电路交换光网络.仿真和实验结果表明,光互连能够为高集成度纳米级芯片提供高带宽、低延迟,小功耗的片内通信服务.     

低功耗千兆光互连链路的研制

基于可编程门阵列(FPGA)器件实现了低功耗的高速光互连链路。采用电时分复用(ETDM)技术在1根光纤上实现了G,数据信号的虚拟并行传输,降低了系统成本。链路物理层带宽达1056Mbit／s,链路稳定传输带宽为545Mbit／s,在应用层可得到300Mbit／s的数据传输率。并通过合理的器件选择、动态功耗管理和低功耗编码等设计方法,使系统功耗降低50％。     

多核之间光互连技术的研究

随着集成电路技术的发展,单个芯片上核的数目不断增加,多核将成为芯片体系架构的未来发展趋势。核间的互连成为芯片设计中的一个关键技术。传统的片上电互连在带宽、时延、能耗和可靠性等方面都面临挑战,光互连可以很好地解决这些问题。本文对现有片上光互连的集成光电子器件发展进行了综述,在此基础上研究了一个典型的多核光互连系统,对网络结构、节点组成和通信过程等逐一进行了分析。结果表明,光互连是未来多核系统的有效互连方式。     

一种云服务器互连芯片交叉开关的设计与实现

在高端云服务器系统中,计算节点间的互连芯片通过Cache一致性协议将多计算节点互连组成分布式和共享内存空间系统,对接口传输速率和路由交换效率要求较高。文中通过分析Cache一致性协议报文的传输特点和互连网络转发需求,设计实现了一种互连芯片的高阶非对称交叉开关。设计通过了系统级的仿真验证,基于FPGA实现的云服务器互连芯片原型验证系统进行了实际带宽测试和芯片带宽匹配优化。互连芯片流片后的系统实测结果表明,满足功能要求,互连网络处理模块延迟8. 75ns,吞吐率65. 03%,达到了设计目标。     

智能化可重构硅光集成器件及芯片应用研究

可重构硅光集成器件和芯片是实现智能化光通信系统的关键技术,其小尺寸、低能耗、低成本、高灵活性等特性为新一代光通信等应用带来了新的发展机遇。总结和讨论了一系列新型热可重构硅光集成器件及芯片,包括可调谐滤波器、光开关代表性功能器件。这些器件及芯片具有设计便捷、工艺简单、兼容等突出优点,被广泛应用于光互连、量子光学和微波光子学等。     

硅基片上复用—解复用技术与器件

近年来,随着云计算、数据中心的迅速发展,光互连凭借其在功耗、速度和带宽等方面具有电互连无可比拟的诸多优势,获得越来越多的关注。为了充分发挥光互连带宽优势,发展波分复用（WDM）、偏振复用（PDM）以及模式复用（MDM）等技术是一种有效途径。而将多种复用方式综合运用则可形成一种多维混合复用技术,从而显著提升光互连通道数量和传输容量。鉴于片上集成（解）复用器是实现多通道并行传输复用系统的关键器件,着重介绍总结了基于硅光子技术实现的超小型片上集成（解）复用器件的进展,包括WDM、PDM、MDM复用—解复用器件以及混合复用—解复用器件。     

基于RapidIO 块数据传输设计与实现

针对航电系统中多芯片间互连通信速率低下的问题,在对RapidIO 互连技术研究的基础上,提出了一种块数据传输方案。以软件异构的方式在交换网络中建立多个实时通信链路,易于系统功能的迁移和重构,采用块数据通信机制实现数据的发送与接收,传输速率相比传统消息机制通信方式有了很大的提升。设计具有很强的通用性和可移植性。     

一种基于新体系结构的 空间固态记录器原型系统

为适应未来对地观测卫星系统对数据吞吐速率和通信带宽的增长需求,本文提出并实现了一种基于新体系结构的,由若干存储模块依靠高速串行互连构成的空间固态记录器原型系统.存储模块采用DDR SDRAM提高吞吐率,配置高速串行接口完成模块间互连,利用单数据总线、双地址总线的存储拓扑结构增加模块内部存储容量,并使用可编程逻辑器件FPGA管理和控制存储资源.同时,应用多层次通信接口协议保证通信链路质量.单模块存储容量可达8GB,访存带宽可达3.2GBps,物理通信带宽高达25Gbps.模块间的高速串行链路误码率可低于10 -11.     

HDMI光缆的研制及自动化测试

给出了一种HDMI光缆连接器制作方式。利用并行光互连技术实现HDMI中4通道高速信号的传输,同时通过编码技术及控制器模拟热插拔过程实现低速互连。通过实际测试,其单通道在3.25 Gbit/s可以传输300 m,可以实现HDMI的长距离传输。HDMI光缆同普通HDMI铜缆一样可热插拔。并且提供了一种自动化测试系统,用于测试并行光互连模块的各个通道,测试系统可以应用到其他的多通道高速光通信产品的测试中,大大降低HDMI光缆的测试成本。     

用MEMS光开关实现高性能光互连网络

建立了1Gbps传输结构的高性能光互连网络，来提高计算机群系统的网络性能。它利用微机电系统(MEMS)光开关和PCI总线全带宽网络接口卡构成光互连链路。全带宽PCI接口卡总线峰值传输速率为132Mbytes／s，光信号传输速率可达1Gbps以上。用MEMS制做的全光开关减少了光—电之间的转换，提供的开关方式与数据的波长、速率和信号格式无关。因而，利用这种网络结构，可以最大限度地减少网络延迟和网络通信开销，极大地提升了机群系统的总体性能。     

Optical fiber interconnection for the scalable parallel computingsystem

In this paper, we discuss the optical fiber interconnection technologies applied in the two types of parallel processing systems: 1) a backplane interconnection in a parallel processor array system and 2) a computing cluster network. We have set up a parallel processor array system using optical fiber to make point-to-point interconnection between processor elements and are developing a low-cost virtual parallel optical fiber interconnection link (VPOFLink) complying with peripheral component interconnect (PCI) local bus specifications for the computing cluster. VPOFLink is integrated with the popular PCI bus interface in order to make the link hold the same bandwidth as that of the PCI bus. It was fabricated as an available peripheral device that can been inserted into the bus slots of commercial computers directly and can operate under the control of PCI bus. Also in this paper, we demonstrate the optical fiber link for a ring network and the architecture of the ring network     

Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

Optical chip-to-chip communication is a promising technology that can mitigate some of the performance short-comings of electrical interconnections, especially bandwidth. Moreover, future high-performance chips are projected to drain hundreds of amperes of supply current. To this end, it is important to develop a high-density and high-performance integrated electrical and optical chip I/O interconnection technology. We describe sea of polymer pillars (or polymer pins), which enables the simultaneous batch fabrication of electrical and optical I/O interconnections at the wafer-level. The electrical and optical I/O interconnections are designed to be laterally compliant to minimize the stresses on the die's low-k dielectric as well as to maintain optical alignment between the coefficient of thermal expansion (CTE)-mismatched board and die during thermal cycling. We demonstrate the fabrication and mechanical performance of various size and aspect ratio electrical and optical polymer pillars. We also describe methods of fabricating polymer pillars with nonflat tip surface area for optical interconnection.     

Breakthrough technologies for the high-performance electrical ATMswitching system

A high-performance electrical asynchronous transfer mode (ATM) switching system is described with the goal of Tb/s ATM switching. The first step system was to use advanced Si-bipolar very large scale integrated (VLSI) technologies and the multichip technique. 1.0 μm bipolar SST technologies and Cu-polyimide multilayer MCM realized a 160 Gb/s throughput ATM system. The performance limitations of the 160 Gb/s system were power supply/cooling and module interconnection. The new ATM switching system, named OPTIMA-1, adopted optical interconnection/distribution to overcome the limitations and achieve 640 Gb/s. The system uses high-performance complementary metal-oxide-semiconductor (CMOS) devices and optical wavelength division multiplexing (WDM) interconnection. Combining OPTIMA-1 with optical cell-by-cell routing functions, i.e., photonic packet routing, can realize variable bandwidth links for 5 Tb/s ATM systems. This paper first reviews high-performance electrical ATM (packet) switching system architecture and hardware technologies. In addition, system limitations are described. Next, the important breakthrough technology of optical WDM interconnection is highlighted. These technologies are adopted to form OPTIMA-1, a prototype of which is demonstrated. The key technologies of the system are advanced 80 Gb/s CMOS/MCM, electrical technologies, and 10 Gb/s, 8 WDM, 8×8 optical interconnection. Details of implementation technologies are also described. Optical cell-by-cell (packet-by-packet) routing is now being studied. From the architectural viewpoint, dynamic link bandwidth sharing will be adopted. In addition, an AWG that performs cell-by-cell routing and a distributed large scale ATM system are realized. Optical routing achieves the 5 Tb/s needed in future B-ISDN ATM backbone systems     

单片集成CMOS光接收前端电路设计

文中采用SMIC 0.18μm CMOS工艺设计了适用于芯片间光互连的的接收机前端放大电路,将跨阻放大器(TIA)和限幅放大器(LA)集成于同一块芯片中.跨阻放大器采用调制型共源共栅(RGC)结构来提高其带宽,限幅放大器采用二阶有源反馈结构和有源电感负载来获得高的增益带宽积.整个接收机前端放大电路具有85dB中频增益,-3dB带宽为4.36GHz.芯片的面积为1mm×0.7mm,在1.8V电源电压下功耗为144mW.     

异地综合试验互联网络技术研究

文中以民用飞机电子系统的试验互联体系为例，介绍了一种试验互联网络设计技术。针对在大型复杂电子系统研发过程中，分布式试验设施之间测试信号传输需满足传输时延和品质保真的要求，采用基于光纤互联网络的多电信号适配技术，通过核心部件光纤交换机和信号中继转换装置构建了可级联扩展的试验互联网络体系。根据对原型系统的测试分析表明，在确保信号传输品质的情况下，在500 m传输范围内试验互联网络对典型信号的延时一般不超过60 μs     

Optical Transceiver Chips Based on Co-Integration of Capacitively Coupled Proximity Interconnects and VCSELs

Combining the strengths of both proximity communication and optical communication, a new hybrid input-output (I/O) platform delivers on-chip bandwidth off-chip and over distance. We demonstrate, for the first time, a four-channel hybrid I/O interface by integrating proximity communication and vertical-cavity surface-emitting-laser-based parallel optical interconnects on the same commercial 90-nm complementary metal-oxide-semiconductor platform. The optical I/O can operate at 5 Gb/s per channel, and the complete hybrid I/O interface achieved 2.5 Gb/s per channel. We characterize the I/O link performance for various data rates and chip separations, and show 10-mum chip separation tolerance for proximity communication     

Low-power network-on-chip for high-performance SoC design

An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-chip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 /spl times/5 mm/sup 2/ chip containing all the above features is fabricated by 0.18-/spl mu/m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.     

Advanced optical interconnection technology in switching equipment

Demands for increased interconnection density and higher bandwidth, coupled with stringent cost constraints of advanced wide bandwidth telecommunication switching equipment, are exhausting conventional electrical interconnection capabilities. The requirement for greater interconnection capabilities, spawned in part by the advances in integrated circuit technologies and the need for enhanced digital services, dictate that technology advancement must occur in traditional electronic packaging and/or interconnection techniques. The resolution of these technological needs is paramount for the successful competitive introduction of these systems. Presently, a “bottle-neck” occurs at the board-to-board level of the interconnection hierarchy. Therefore, an opportunity exists for the development of new optical interconnection techniques which can be incorporated into system designs beginning at this interconnection level and beyond. The strategic insertion of optical interconnection technology into these electronic processing systems not only meets projected performance requirements, but potentially offers them at a competitive cost. This paper describes some of the new optical strategies switching equipment designers are incorporating into today's products. These strategies range from optical data links to an implementation of a flexible optical backplane called OptiFlex