Neuron MOS binary-logic integrated circuits. II. Simplifyingtechniques of circuit configuration and their practicalapplications

For pt.I see ibid., vol.40, no.3, p.570-6 (March 1993). The fundamental circuit ideas developed by the authors in Part I are applied to practical circuits, and the impact of neuron MOSFET on the implementation of binary-logic circuits is examined. For this purpose, two techniques are presented to simplify the circuit configurations. It is shown that the input-stage D/A converter circuit in the basic configuration can be eliminated without any major problems, resulting in improved noise margins and speed performance. Then a design technique for symmetric functions, which is especially important when the number of input variables increases, is presented. The νMOS logic design is characterized by a large reduction in the number of transistors as well as of interconnections. However, the decrease in transistor count comes at a cost in process tolerance due to the multivalued nature of the device operation. Test circuits were fabricated by a typical double-polysilicon CMOS process, and the measurement results are presented     

Protective device for MOS integrated circuits

Two protective devices for MOS integrated circuits have been extensively tested and proved feasible. They also perform more reliably than conventional Zener diodes. One of them has been used in the fabrication of a dual 25-bit MOS and MNOS integrated shift register and performed reliably.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

Calculator-aided design of MOS integrated circuits

A set of programs has been developed for the characterization of the d.c. and transient behavior of MOS integrated circuits. The d.c. analysis program calculates and plots the voltage transfer and power dissipation characteristic of a MOS inverter approached from a new point of view. The algorithm enables the characterization of basic MOS IC cells on desktop calculators. The program for the transient characterization calculates and plots the output waveform of three simple MOS cells most often occurring in MOS IC's.The MOS transistor is simulated in terms of a four-terminal large signal model described by device processing parameters. Complex MOS IC's can be also characterized by appropriate combining of these programs.     

Design and implementation of all MOS micro-power voltage reference circuit

In this work we are proposing the all MOST based reference voltage generating circuit, which utilizes the classical principle of addition of two voltages with opposite temperature coefficients. The targeted application of the proposed circuit is a low-dropout regulator which is used in a RF energy harvesting system. The proposed voltage reference circuit is implemented using a standard 0.18 μm CMOS technology. It generates the average reference voltage of 543.658 mV with an average temperature coefficient of 17.43 ppm/°C in the temperature range of ?40 to +85 °C, for the operating supply voltage ranging from 1.25 to 2 V. The maximum power consumption of the proposed architecture is ≈1.5 μW, including power dissipation in bias circuitry and the reference voltage generating core at 2 V supply voltage. The averaged measured line regulation is 1.642 mV/V. The measured power-supply rejection ratio without any filtering capacitor at 100 Hz and 1 MHz are ?62.24 and ?18.94 dB, respectively. Additionally, the measured noise density without any filtering capacitor at 10 Hz and 100 KHz is 20.54 and \(0.30\,\upmu \hbox {V}/\sqrt{\hbox{Hz}}\) , respectively. The proposed circuit has silicon area of ≈0.007 mm².     

Harmonic performance of single-channel MOS integrated circuits

Using simple square-law models for both the MOSFET current-voltage characteristics and the relationship between the threshold voltage and the source-to-substrate voltage, simple expressions are presented for predicting the performance of the basic MOSFET circuits used in analog MOS technology. Using these expressions, the low-frequency gain and the second and third harmonic distortion performance of the enhancement-load inverters, enhancement-load source follower, depletion-load inverter, and depletion-load source follower can be easily predicted by hand calculations. The results obtained by using these expressions are compared with previously published measurements and calculations.     

Harmonic distortion in single-channel MOS integrated circuits

Expressions assuming a simple square-law MOSFET model are presented for the low-frequency harmonic distortion of an enhancement-mode source follower. These theoretical results are compared to measurements of several integrated versions of the three circuit types. For a given fabrication process, the main factors determining the amount of distortion for all three circuits are the quiescent output voltage and the output swing; to a first order, the distortion does not depend on bias current or device geometries. The distortion of an enhancement-mode source follower has a similar behavior to that of an enhancement-load inverter with the same output quiescent voltage and output swing; both distortions are nearly proportional to the body-effect coefficient. For the same output quiescent voltage and output swing, the distortion of the depletion-load inverter is the highest among the three circuits, but is practically independent of process parameters.     

Methodology for the design of a 4-bit soft-hardware-logic circuit based on neuron MOS transistors

As soft-hardware-logic circuits had been proposed in the literature as an alternative for digital circuits taking advantage the fact that any Boolean function could be implemented with the same cell, just configuring external signals, this work shows a methodology that could be followed particularly for the design of a four bits logic gate, using the so-called neuron MOS transistor (ν-MOS). Simulation results show the feasibility of the design for performing as XNOR, NOR, OR, XOR, AND or NAND logic gates, for instance. In order to extrapolate the design to a higher number of bits, the key issue is to properly consider the weight of the input capacitances in correlation with the number of input bits. A D/A converter can be used as the input stage of the configuration. This design considers the D/A converter-less version, since it helps to increase device integration as the number of transistors used is reduced with no difference in its performance. The design should be based on the theoretical floating potential diagram (FPD) of the desired logic gate.     

An optimized output stage for MOS integrated circuits

An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data is also presented which allows a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.     

Potential of MOS technologies for analog integrated circuits

Reviews the rapid progress in MOS analog circuit techniques over the past three years, and attempts to estimate the near-term attainable characteristics of MOS LSI circuits which incorporate both analog and digital functions.     

Shielded silicon gate complementary MOS integrated circuit

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift inC-Vcurve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.     

Technology and performance of integrated complementary MOS circuits

The desirable characteristics of complementary MOS circuits are low standby power consumption, high speed, and high noise immunity. These require close control and matching of n- and p-channel transistor characteristics. Acceptable limits for mismatch between devices were derived based on circuit considerations and were related to process variables. Predicted performances were achieved using test circuits; feasibility of the technology has been shown. The reliability of fabricated test structures was evaluated.     

VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor.A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.     

Analysis of harmonic distortion in single-channel MOS integrated circuits

Presents a general analysis for the calculation of harmonic distortion in single-channel monolithic analog MOS integrated circuits. Power series expressions are obtained for basic stages often used in an analog MOS technology. These include the depletion load inverter, enhancement load inverter, depletion load source follower, enhancement load source follower, and the differential pair. From the power series expressions, the second-order harmonic distortion is calculated. These results are compared with data obtained from a test chip.     

Behavior of analog MOS integrated circuits at high temperatures

Thermal effects on small-signal characteristics of MOS transistors are studied and parameters of MOS amplifiers operating at high temperatures are calculated. The predicted performance has been experimentally verified and high-temperature measurements of an operational amplifier and a switched-capacitor precision amplifier are presented.     

Computer-aided design and characterization of digital MOS integrated circuits

A computer-aided circuit-simulation method is developed to enable the design, characterization, and optimization of MOS integrated circuits. The computation of dc and transient characteristics is done in terms of physical device parameters extracted from processing information and incorporated in an analytical device model. It is demonstrated that any MOS circuit configuration (with its associated series resistances and parasitic devices) can be analyzed in terms of an equivalent inverter. Input-output transfer characteristics are obtained by superposition of the load and transistor I-V characteristics, providing the necessary information for dc > `worst-case' design. A simple device model was used to compute circuit transient response. All the computed characteristics are in good agreement with measurements performed on integrated circuits.     

神经MOS晶体管

神经ＭＯＳ晶体管是１９９１年发明出来的一种具有高功能度的多输入栅控制的浮栅ＭＯＳ器件。本文介绍了它的基本结构和特点,论述了这种新哭喊 件及其电路的国外研究现状、研究趋以及笔者所完成的研究工作。     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.