基于Y和Z参数表征的微波SiGe HBT小信号模型参数提取

High frequency intrinsic small-signal model parameter extraction for microwave SiGe heterojunction bipolar transistors is studied, with a focus on the main feedback elements including the emitter series resistor, internal and external base-collector capacitors as well as the base series resistor, all of which are important in determining the behavior of the device equivalent circuit. In accordance with the respective features of definition of the Y- and Z-parameters, a novel combined use of them succeeds in reasonably simplifying the device equivalent circuit and thus decoupling the extraction of base-collector capacitances from other model parameters. As a result, a very simple direct extraction method is proposed. The proposed method is applied for determining the SiGe HBT small-signal model parameters by taking numerically simulated Y- and Z-parameters as nominal ＂measurement data＂ with the help of a Taurus-device simulator. The validity of the method is preliminarily confirmed by the observation of certain linear relations of device frequency behavior as predicted by the corresponding theoretical analysis. Furthermore, the extraction results can be used to reasonably account for the dependence of the extracted model parameters on device geometry and process parameters, reflecting the explicit physical meanings of parameters, and especially revealing the distributed nature of the base series resistor and its complex interactions with base-collector capacitors. Finally, the accuracy of our model parameter extraction method is further validated by comparing the modeled and simulated S-parameters as a function of frequency.     

SDD定义的InP DHBT大信号模型

A self-built accurate and flexible large-signal model based on an analysis of the characteristics of InP double heterojunction bipolar transistors （DHBTs） is implemented as a seven-port symbolically defined device （SDD） in Agilent ADS. The model accounts for most physical phenomena incluuing the self-heating effect, Kirk effect, soft knee effect, base collector capacitance and collector transit time. The validity and the accuracy of the large-signal model are assessed by comparing the simulation with the measurement of DC, multi-bias small signal S parameters for InP DHBTs.     

基区重掺杂禁带变窄效应在突变HBT器件模拟中的准确考虑

Heavy doping of the base in HBTs brings about a bandgap narrowing （BGN） effect, which modifies the intrinsic carrier density and disturbs the band offset, and thus leads to the change of the currents. Based on a thermionic-field-diffusion model that is used to the analyze the performance of an abrupt HBT with a heavydoped base, the conclusion is made that, although the BGN effect makes the currents obviously change due to the modification of the intrinsic carrier density, the band offsets disturbed by the BGN effect should also be taken into account in the analysis of the electrical characteristics of abrupt HBTs. In addition, the BGN effect changes the bias voltage for the onset of Kirk effects.     

Modeling and simulation of nanoscale tri-gate MOSFETs including quantum effects

Quantum effects are predominant in tri-gate MOSFETs, so a model should be developed. For the first time, this paper presents the analytical model for quantization effects of thin film silicon tri-gate MOSFETs by using variational approach. An analytical expression of the inversion charge distribution function（ICDF） or wave function for the tri-gate MOSFETs has been obtained. This obtained ICDF is used to calculate the important device parameters, such as the inversion charge centroid and inversion charge density. The results are validated against with the simulation data.     

多层浮栅FET pH传感单元阈值电压敏感模型分析和讨论

Research into new pH sensors fabricated by the standard CMOS process is currently a hot topic. The new pH sensing multi-floating gate field effect transistor is found to have a very large threshold voltage, which is different from the normal ion-sensitive field effect transistor. After analyzing all the interface layers of the structure, a new sensitive model based on the Gauss theorem and the charge neutrality principle is created in this paper. According to the model, the charge trapped on the multi-floating gate during the process and the thickness of the sensitive layer are the main causes of the large threshold voltage. From this model, it is also found that removing the charge on the multi-floating gate is an effective way to decrease the threshold voltage. The test results for three different standard pH buffer solutions show the correctness of the model and point the way to solve the large threshold problem.     

带有自测试电路的10GSps 8bit DAC设计

We present a 10 Gsps 8 bit digital-to-analog converter （DAC） with a novel built-in self-test （BIST） circuit, which makes it possible to evaluate the DAC＇s performance without a complicated test setup. Design con- siderations and test results are included. According to the test results, the DAC core and the BIST circuit are able to work under 10 GHz. The chip is fabricated in 0.18μm SiGe HBTs with ft of 100 GHz. The DAC core occupies a die size of 260 × 250μm^2.     

High Power SiGe X-Band (8～10GHz) Heterojunction Bipolar Transistors and Amplifiers

Limited by increased parasitics and thermal effects as device size increases,current commercial SiGe power HBTs are difficult to operate at X-band (8～12GHz) frequencies with adequate power added efficiencies at high power levels.We find that,by changing the heterostructure and doping profile of SiGe HBTs,their power gain can be significantly improved without resorting to substantial lateral scaling.Furthermore,employing a common-base configuration with a proper doping profile instead of a common-emitter configuration improves the power gain characteristics of SiGe HBTs,thus permitting these devices to be efficiently operated at X-band frequencies.In this paper,we report the results of SiGe power HBTs and MMIC power amplifiers operating at 8～10GHz.At 10GHz,a 22.5dBm (178mW) RF output power with a concurrent gain of 7.32dB is measured at the peak power-added efficiency of 20.0%,and a maximum RF output power of 24.0dBm (250mW) is achieved from a 20 emitter finger SiGe power HBT.The demonstration of a single-stage X-band medium-power linear MMIC power amplifier is also realized at 8GHz.Employing a 10-emitter finger SiGe HBT and on-chip input and output matching passive components,a linear gain of 9.7dB,a maximum output power of 23.4dBm,and peak power added efficiency of 16% are achieved from the power amplifier.The MMIC exhibits very low distortion with 3rd order intermodulation (IM) suppression C/I of -13dBc at an output power of 21.2dBm and over 20dBm 3rd order output intercept point (OIP3).     

电流模线性控制电荷泵的研究与设计

To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.     

一种宽带的InGaP/GaAs HBT 再生频率分频器

A dynamic divide-by-two regenerative GaP/GaAs heterojunction bipolar transistors （HBTs） frequency divider （RFD） is presented in a 60-GHz-fT Intechnology. To achieve high operation bandwidth, active loads instead of resistor loads are incorporated into the RFD. On-wafer measurement shows that the divider is operating from 10 GHz up to at least 40 GHz, limited by the available input frequency. The maximum operation frequency of the divider is found to be much higher than fT/2 of the transistor, and also the divider has excellent input sensitivity. The divider consumes 300.85 mW from 5 V supply and occupies an area of 0.47 × 0.22 mm^2.     

An improved large signal model of InP HEMTs

An improved large signal model for InP HEMTs is proposed in this paper.The channel current and charge model equations are constructed based on the Angelov model equations.Both the equations for channel current and gate charge models were all continuous and high order drivable,and the proposed gate charge model satisfied the charge conservation.For the strong leakage induced barrier reduction effect of InP HEMTs,the Angelov current model equations are improved.The channel current model could fit DC performance of devices.A 2 × 25μm × 70 nm InP HEMT device is used to demonstrate the extraction and validation of the model,in which the model has predicted the DC I-V,C-Vand bias related S parameters accurately.     

基于一种新架构的4GH 32比特的直接数字频率合成器

This paper presents a novel direct digital frequency synthesizer(DDFS)architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method,which has the advantages of high speed,low power and low hardware resources.By subdividing the sinusoid into a collection of phase segments,the same initial value of each segment is realized by a nonlinear DAC.The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method.Then,the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment.Meanwhile,the fine ROM stores the differences between the line values and the initial value of each line.A ROM compression ratio of32 can be achieved in the case of 11 bit phase and 9 bit amplitude.Based on the above method,a prototype chip was fabricated using 1.4 m GaAs HBT technology.The measurement shows an average spurious-free dynamic range(SFDR)of 45 dBc,with the worst SFDR only 40.07 dBc at a 4.0 GHz clock.The chip area is 4.6 3.7 mm2and it consumes 7 W from a–4.9 V power supply.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.